Laurent Pinchart wrote:
> It's a Rev. D.3
Hmmmm....I regularly use one of those for testing (maybe it's an 855T),
and it seems OK for me. The first one I had didn't work well, but
it was tracked down to a UPM/SDRAM timing problem. People keep talking
about running > 50 MHz bus on these newer parts, is there something
different about the memory controller that allows this and may cause
compatibility problems? I have (fortunately :-) not looked at this
level of detail in the newer parts.
When you disable copyback you also disable burst mode write from
the CPU core.
-- Dan
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