I've got a Xilinx ZCU102 with a macb driver from xilinx's 2017.3 branch
which has 4.9 linux kernel and PTP support).
I believe I've got the necessary bits built into the kernel (kernel options
shown below).
I'm trying to run as a slave, but it looks like its not working. I'd
appreciate any and all advice, as I'm at wits end.
ptp4l -i eth0 -m -s
ptp4l[13.741]: selected /dev/ptp0 as PTP clock
ptp4l[13.741]: driver changed our HWTSTAMP options
ptp4l[13.741]: tx_type 1 not 1
ptp4l[13.741]: rx_filter 1 not 12
ptp4l[13.742]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[13.742]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[21.640]: driver changed our HWTSTAMP options
ptp4l[21.640]: tx_type 1 not 1
ptp4l[21.640]: rx_filter 1 not 12
ptp4l[21.640]: selected best master clock 000a35.fffe.002201
ptp4l[29.520]: driver changed our HWTSTAMP options
ptp4l[29.520]: tx_type 1 not 1
ptp4l[29.520]: rx_filter 1 not 12
ptp4l[29.520]: selected best master clock 000a35.fffe.002201
ptp4l[29.688]: port 1: new foreign master 003064.fffe.1982cd-1
ptp4l[33.786]: selected best master clock 003064.fffe.1982cd
ptp4l[33.786]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[34.810]: master offset 651262704418 s0 freq +0 path delay 0
ptp4l[35.834]: master offset 649867375548 s0 freq +0 path delay 346072539
ptp4l[36.859]: master offset 648818118960 s0 freq +0 path delay 346072539
ptp4l[37.883]: master offset 647714697182 s0 freq +0 path delay 400129313
ptp4l[38.908]: master offset 646665287635 s0 freq +0 path delay 400129313
ptp4l[39.933]: master offset 645623541219 s0 freq +0 path delay 392486789
ptp4l[40.957]: master offset 644575797496 s0 freq +0 path delay 390867813
ptp4l[41.982]: master offset 643526460652 s0 freq +0 path delay 390867813
It's almost like timestamps aren't happening in the driver.
However, the driver appears to have all of the proper options:
# ethtool -T eth0
Time stamping parameters for eth0:
Capabilities:
hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
PTP Hardware Clock: 0
Hardware Transmit Timestamp Modes:
off (HWTSTAMP_TX_OFF)
on (HWTSTAMP_TX_ON)
Hardware Receive Filter Modes:
none (HWTSTAMP_FILTER_NONE)
all (HWTSTAMP_FILTER_ALL)
Here are my kernel options.
First, the easy ones:
CONFIG_NETWORK_PHY_TIMESTAMPING
CONFIG_PPS
CONFIG_PTP_1588_CLOCK
I've also found other variables online in various places that I felt need
to be set for this board:
CONFIG_DP83640_PHY (because it has this PHY onboard, the TI DP83640)
I've also been told I need to enable the Common Clock, so I've done that,
though there's nothing in the linuxptp documentation about that.
CONFIG_COMMON_CLK
CONFIG_COMMON_CLK_ZYNQMP
This next one had to do with common clock support in ARM reference designs,
but I don't know if the ultrazinq uses the SP810 system controller. Better
to be safe than sorry, right?
CONFIG_CLK_SP810
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