================
@@ -8731,22 +8698,33 @@ ParseStatus
AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
MCRegister SecondReg;
Res = tryParseScalarRegister(SecondReg);
if (!Res.isSuccess())
- return Error(E, "expected second odd register of a consecutive same-size "
- "even/odd register pair");
+ return Error(E, IsXZRPair ? "expected second xzr in xzr/xzr register pair"
+ : SecondRegExpected);
+
+ // For SYSP, Rt == 31 denotes the optional-pair default. If the explicit
+ // pair starts with xzr, the derived second register must be xzr too.
+ if (IsXZRPair) {
+ if (!XRegClass.contains(SecondReg) || SecondReg != AArch64::XZR)
+ return Error(E, "expected second xzr in xzr/xzr register pair");
+ Operands.push_back(AArch64Operand::CreateReg(AArch64::XZR, RegKind::Scalar,
----------------
jthackray wrote:
Done. The `xzr, xzr` case now parses to an artificial `XZR_XZR` pair register
and is emitted as the `SyspPairsClass` operand. Disassembly and the default
alias use this too.
https://github.com/llvm/llvm-project/pull/182410
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