================
@@ -8701,26 +8670,24 @@ ParseStatus
AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
MCRegister FirstReg;
ParseStatus Res = tryParseScalarRegister(FirstReg);
if (!Res.isSuccess())
- return Error(S, "expected first even register of a consecutive same-size "
- "even/odd register pair");
+ return Error(S, FirstRegExpected);
const MCRegisterClass &WRegClass =
AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
const MCRegisterClass &XRegClass =
AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
- bool isXReg = XRegClass.contains(FirstReg),
- isWReg = WRegClass.contains(FirstReg);
- if (!isXReg && !isWReg)
- return Error(S, "expected first even register of a consecutive same-size "
- "even/odd register pair");
+ bool IsXZRPair = AllowXZRPair && FirstReg == AArch64::XZR;
+ bool IsXReg = XRegClass.contains(FirstReg);
+ bool IsWReg = !AllowXZRPair && WRegClass.contains(FirstReg);
+ if (!IsXZRPair && !IsXReg && !IsWReg)
+ return Error(S, FirstRegExpected);
----------------
jthackray wrote:
Implemented something very similar, but with a slightly more readable `if()`
logic
https://github.com/llvm/llvm-project/pull/182410
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