Author: dsanders Date: Mon Apr 27 07:08:26 2015 New Revision: 235869 URL: http://llvm.org/viewvc/llvm-project?rev=235869&view=rev Log: Merging r229675: ------------------------------------------------------------------------ r229675 | vkalintiris | 2015-02-18 14:57:05 +0000 (Wed, 18 Feb 2015) | 7 lines
[mips] Avoid redundant sign extension of the result of binary bitwise instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7581 ------------------------------------------------------------------------ Modified: llvm/branches/release_36/ (props changed) llvm/branches/release_36/lib/Target/Mips/Mips64InstrInfo.td llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/and.ll llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/or.ll llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/xor.ll Propchange: llvm/branches/release_36/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Mon Apr 27 07:08:26 2015 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,226023,226029,226044,226046,226048,226058,226075,226151,226164-226166,226170-226171,226182,226407-226409,226473,226588,226616,226652,226664,226708,226711,226755,226791,226808-226809,226905,227005,227084-227085,227087,227089,227250,227260-227261,227269,227290,227294,227299,227319,227339,227430,227491,227584,227603,227628,227670,227809,227815,227903,227934,227972,227983,228049,228129,228168,228331,228411,228444,228490,228500,228507,228518,228525,228565,228656,228760-228761,228793,228842,228899,228957,228969,228979,229029,229343,229351-229352,229421,229495,229529,229731,229911,230058,231219,231227,231563,231601,232046,232085,232189 +/llvm/trunk:155241,226023,226029,226044,226046,226048,226058,226075,226151,226164-226166,226170-226171,226182,226407-226409,226473,226588,226616,226652,226664,226708,226711,226755,226791,226808-226809,226905,227005,227084-227085,227087,227089,227250,227260-227261,227269,227290,227294,227299,227319,227339,227430,227491,227584,227603,227628,227670,227809,227815,227903,227934,227972,227983,228049,228129,228168,228331,228411,228444,228490,228500,228507,228518,228525,228565,228656,228760-228761,228793,228842,228899,228957,228969,228979,229029,229343,229351-229352,229421,229495,229529,229675,229731,229911,230058,231219,231227,231563,231601,232046,232085,232189 Modified: llvm/branches/release_36/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/Mips/Mips64InstrInfo.td?rev=235869&r1=235868&r2=235869&view=diff ============================================================================== --- llvm/branches/release_36/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/branches/release_36/lib/Target/Mips/Mips64InstrInfo.td Mon Apr 27 07:08:26 2015 @@ -428,6 +428,14 @@ def : MipsPat<(trunc (assertzext GPR64:$ def : MipsPat<(i32 (trunc GPR64:$src)), (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; +// Bypass trunc nodes for bitwise ops. +def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))), + (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>; +def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))), + (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; +def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))), + (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; + // 32-to-64-bit extension def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; Modified: llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/and.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/and.ll?rev=235869&r1=235868&r2=235869&view=diff ============================================================================== --- llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/and.ll (original) +++ llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/and.ll Mon Apr 27 07:08:26 2015 @@ -51,10 +51,7 @@ define signext i32 @and_i32(i32 signext entry: ; ALL-LABEL: and_i32: - ; GP32: and $2, $4, $5 - - ; GP64: and $[[T0:[0-9]+]], $4, $5 - ; GP64: sll $2, $[[T0]], 0 + ; ALL: and $2, $4, $5 %r = and i32 %a, %b ret i32 %r Modified: llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/or.ll?rev=235869&r1=235868&r2=235869&view=diff ============================================================================== --- llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/or.ll (original) +++ llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/or.ll Mon Apr 27 07:08:26 2015 @@ -51,11 +51,7 @@ define signext i32 @or_i32(i32 signext % entry: ; ALL-LABEL: or_i32: - ; GP32: or $2, $4, $5 - - ; GP64: or $[[T0:[0-9]+]], $4, $5 - ; FIXME: The sll instruction below is redundant. - ; GP64: sll $2, $[[T0]], 0 + ; ALL: or $2, $4, $5 %r = or i32 %a, %b ret i32 %r Modified: llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/xor.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/xor.ll?rev=235869&r1=235868&r2=235869&view=diff ============================================================================== --- llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/xor.ll (original) +++ llvm/branches/release_36/test/CodeGen/Mips/llvm-ir/xor.ll Mon Apr 27 07:08:26 2015 @@ -51,10 +51,7 @@ define signext i32 @xor_i32(i32 signext entry: ; ALL-LABEL: xor_i32: - ; GP32: xor $2, $4, $5 - - ; GP64: xor $[[T0:[0-9]+]], $4, $5 - ; GP64: sll $2, $[[T0]], 0 + ; ALL: xor $2, $4, $5 %r = xor i32 %a, %b ret i32 %r _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
