Author: dsanders Date: Mon Apr 27 07:15:29 2015 New Revision: 235870 URL: http://llvm.org/viewvc/llvm-project?rev=235870&view=rev Log: Merging r230235: ------------------------------------------------------------------------ r230235 | dsanders | 2015-02-23 17:22:16 +0000 (Mon, 23 Feb 2015) | 16 lines
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 ------------------------------------------------------------------------ Added: llvm/branches/release_36/test/CodeGen/Mips/no-odd-spreg-msa.ll - copied unchanged from r230235, llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll Modified: llvm/branches/release_36/ (props changed) llvm/branches/release_36/lib/Target/Mips/MipsRegisterInfo.td llvm/branches/release_36/lib/Target/Mips/MipsSEISelLowering.cpp Propchange: llvm/branches/release_36/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Mon Apr 27 07:15:29 2015 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,226023,226029,226044,226046,226048,226058,226075,226151,226164-226166,226170-226171,226182,226407-226409,226473,226588,226616,226652,226664,226708,226711,226755,226791,226808-226809,226905,227005,227084-227085,227087,227089,227250,227260-227261,227269,227290,227294,227299,227319,227339,227430,227491,227584,227603,227628,227670,227809,227815,227903,227934,227972,227983,228049,228129,228168,228331,228411,228444,228490,228500,228507,228518,228525,228565,228656,228760-228761,228793,228842,228899,228957,228969,228979,229029,229343,229351-229352,229421,229495,229529,229675,229731,229911,230058,231219,231227,231563,231601,232046,232085,232189 +/llvm/trunk:155241,226023,226029,226044,226046,226048,226058,226075,226151,226164-226166,226170-226171,226182,226407-226409,226473,226588,226616,226652,226664,226708,226711,226755,226791,226808-226809,226905,227005,227084-227085,227087,227089,227250,227260-227261,227269,227290,227294,227299,227319,227339,227430,227491,227584,227603,227628,227670,227809,227815,227903,227934,227972,227983,228049,228129,228168,228331,228411,228444,228490,228500,228507,228518,228525,228565,228656,228760-228761,228793,228842,228899,228957,228969,228979,229029,229343,229351-229352,229421,229495,229529,229675,229731,229911,230058,230235,231219,231227,231563,231601,232046,232085,232189 Modified: llvm/branches/release_36/lib/Target/Mips/MipsRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/Mips/MipsRegisterInfo.td?rev=235870&r1=235869&r2=235870&view=diff ============================================================================== --- llvm/branches/release_36/lib/Target/Mips/MipsRegisterInfo.td (original) +++ llvm/branches/release_36/lib/Target/Mips/MipsRegisterInfo.td Mon Apr 27 07:15:29 2015 @@ -388,6 +388,8 @@ def MSA128W: RegisterClass<"Mips", [v4i3 (sequence "W%u", 0, 31)>; def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, (sequence "W%u", 0, 31)>; +def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128, + (decimate (sequence "W%u", 0, 31), 2)>; def MSACtrl: RegisterClass<"Mips", [i32], 32, (add MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; Modified: llvm/branches/release_36/lib/Target/Mips/MipsSEISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/Mips/MipsSEISelLowering.cpp?rev=235870&r1=235869&r2=235870&view=diff ============================================================================== --- llvm/branches/release_36/lib/Target/Mips/MipsSEISelLowering.cpp (original) +++ llvm/branches/release_36/lib/Target/Mips/MipsSEISelLowering.cpp Mon Apr 27 07:15:29 2015 @@ -2883,10 +2883,21 @@ emitCOPY_FW(MachineInstr *MI, MachineBas unsigned Ws = MI->getOperand(1).getReg(); unsigned Lane = MI->getOperand(2).getImm(); - if (Lane == 0) - BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo); - else { - unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + if (Lane == 0) { + unsigned Wt = Ws; + if (!Subtarget.useOddSPReg()) { + // We must copy to an even-numbered MSA register so that the + // single-precision sub-register is also guaranteed to be even-numbered. + Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); + + BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws); + } + + BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); + } else { + unsigned Wt = RegInfo.createVirtualRegister( + Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass : + &Mips::MSA128WEvensRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane); BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); @@ -2948,7 +2959,9 @@ MipsSETargetLowering::emitINSERT_FW(Mach unsigned Wd_in = MI->getOperand(1).getReg(); unsigned Lane = MI->getOperand(2).getImm(); unsigned Fs = MI->getOperand(3).getReg(); - unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + unsigned Wt = RegInfo.createVirtualRegister( + Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass : + &Mips::MSA128WEvensRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) .addImm(0) _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
