================
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector<MCPhysReg> ReservedHi = {
----------------
arsenm wrote:
What kind of failures? AMDGPU also has synthetic 16-bit high sub registers and
they are not explicitly reserved. Are you adding these to an allocatable class?
https://github.com/llvm/llvm-project/pull/114263
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