[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

[Matt Arsenault via llvm-branch-commits]

================
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const 
MachineFunction &MF,
   return {};
 }
 
+static SmallVector<MCPhysReg> ReservedHi = {
----------------
arsenm wrote:

But what are the actual failures, messages, location?  If the high half of 
register isn't allocatable / addressable in the first place, it shouldn't just 
appear to cause issues 

https://github.com/llvm/llvm-project/pull/114263
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits