https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/177418
Avoid introducing fminnum_ieee/fmaxnum_ieee on f16 if f16 is not legal. This avoids regressing minimum/maximum cases in a future commit. >From c29b2bbdb19801d1523209a0a485ae7484400cd2 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Thu, 22 Jan 2026 18:31:29 +0100 Subject: [PATCH] AMDGPU: Avoid introducing illegal fminnum_ieee/fmaxnum_ieee Avoid introducing fminnum_ieee/fmaxnum_ieee on f16 if f16 is not legal. This avoids regressing minimum/maximum cases in a future commit. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 0ba66af9bd41c..69d73975bf9ef 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -15273,8 +15273,9 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N, // for some types, but at a higher cost since it's implemented with a 3 // operand form. const SDNodeFlags Flags = N->getFlags(); - if ((Opc == ISD::FMINIMUM || Opc == ISD::FMAXIMUM) && - !Subtarget->hasIEEEMinimumMaximumInsts() && Flags.hasNoNaNs()) { + if ((Opc == ISD::FMINIMUM || Opc == ISD::FMAXIMUM) && Flags.hasNoNaNs() && + !Subtarget->hasIEEEMinimumMaximumInsts() && + isOperationLegal(ISD::FMINNUM_IEEE, VT.getScalarType())) { unsigned NewOpc = Opc == ISD::FMINIMUM ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; return DAG.getNode(NewOpc, SDLoc(N), VT, Op0, Op1, Flags); _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
