llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-globalisel Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Avoid introducing fminnum_ieee/fmaxnum_ieee on f16 if f16 is not legal. This avoids regressing minimum/maximum cases in a future commit. --- Full diff: https://github.com/llvm/llvm-project/pull/177418.diff 1 Files Affected: - (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+3-2) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 0ba66af9bd41c..69d73975bf9ef 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -15273,8 +15273,9 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N, // for some types, but at a higher cost since it's implemented with a 3 // operand form. const SDNodeFlags Flags = N->getFlags(); - if ((Opc == ISD::FMINIMUM || Opc == ISD::FMAXIMUM) && - !Subtarget->hasIEEEMinimumMaximumInsts() && Flags.hasNoNaNs()) { + if ((Opc == ISD::FMINIMUM || Opc == ISD::FMAXIMUM) && Flags.hasNoNaNs() && + !Subtarget->hasIEEEMinimumMaximumInsts() && + isOperationLegal(ISD::FMINNUM_IEEE, VT.getScalarType())) { unsigned NewOpc = Opc == ISD::FMINIMUM ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE; return DAG.getNode(NewOpc, SDLoc(N), VT, Op0, Op1, Flags); `````````` </details> https://github.com/llvm/llvm-project/pull/177418 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
