https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/194813
>From 2f7e57912ce53d3a25eafb402ef8ab5385b4f7c3 Mon Sep 17 00:00:00 2001 From: Aaditya <[email protected]> Date: Tue, 28 Apr 2026 15:48:13 +0530 Subject: [PATCH] [AMDGPU] Support Wave Reduction for true-16 types - 3 Supporting true-16 versions of the reduction intrinsics Supported Ops: `and`, `or`, `xor`. Supports only the iterative stratergy, DPP is yet to be supported. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 23 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 5 +- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll | 371 ++++++++++----- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll | 371 ++++++++++----- .../CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll | 433 ++++++++++++------ 5 files changed, 812 insertions(+), 391 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index e28ba26563147..77511ea97e3bc 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5632,6 +5632,7 @@ static uint64_t getIdentityValueForWaveReduction(unsigned Opc) { case AMDGPU::V_MIN_U16_fake16_e64: case AMDGPU::V_MIN_U16_t16_e64: case AMDGPU::V_AND_B16_fake16_e64: + case AMDGPU::V_AND_B16_t16_e64: return 0xffff; case AMDGPU::V_MIN_I16_e64: case AMDGPU::V_MIN_I16_opsel_e64: @@ -5649,7 +5650,9 @@ static uint64_t getIdentityValueForWaveReduction(unsigned Opc) { case AMDGPU::V_ADD_I16_t16_e64: case AMDGPU::V_SUB_I16_t16_e64: case AMDGPU::V_OR_B16_fake16_e64: + case AMDGPU::V_OR_B16_t16_e64: case AMDGPU::V_XOR_B16_fake16_e64: + case AMDGPU::V_XOR_B16_t16_e64: return 0x0; case AMDGPU::V_MAX_I16_e64: case AMDGPU::V_MAX_I16_opsel_e64: @@ -5721,8 +5724,11 @@ static bool is16bitWaveReduceOperation(unsigned Opc) { Opc == AMDGPU::V_SUB_I16_e64 || Opc == AMDGPU::V_SUB_I16_fake16_e64 || Opc == AMDGPU::V_ADD_I16_t16_e64 || Opc == AMDGPU::V_SUB_I16_t16_e64 || Opc == AMDGPU::V_AND_B16_fake16_e64 || + Opc == AMDGPU::V_AND_B16_t16_e64 || Opc == AMDGPU::V_OR_B16_fake16_e64 || - Opc == AMDGPU::V_XOR_B16_fake16_e64; + Opc == AMDGPU::V_OR_B16_t16_e64 || + Opc == AMDGPU::V_XOR_B16_fake16_e64 || + Opc == AMDGPU::V_XOR_B16_t16_e64; } static bool is32bitWaveReduceOperation(unsigned Opc) { @@ -5890,8 +5896,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, case AMDGPU::S_MAX_I32: case AMDGPU::V_MAX_F32_e64: case AMDGPU::V_AND_B16_fake16_e64: - case AMDGPU::V_OR_B16_fake16_e64: + case AMDGPU::V_AND_B16_t16_e64: case AMDGPU::S_AND_B32: + case AMDGPU::V_OR_B16_fake16_e64: + case AMDGPU::V_OR_B16_t16_e64: case AMDGPU::S_OR_B32: { // Idempotent operations. BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg); @@ -5914,6 +5922,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, break; } case AMDGPU::V_XOR_B16_fake16_e64: + case AMDGPU::V_XOR_B16_t16_e64: case AMDGPU::S_XOR_B32: case AMDGPU::S_XOR_B64: case AMDGPU::V_ADD_I16_e64: @@ -5950,6 +5959,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, switch (Opc) { case AMDGPU::V_XOR_B16_fake16_e64: + case AMDGPU::V_XOR_B16_t16_e64: case AMDGPU::S_XOR_B32: case AMDGPU::S_XOR_B64: { // Performing an XOR operation on a uniform value @@ -5963,7 +5973,8 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI, .addReg(NewAccumulator->getOperand(0).getReg()) .addImm(1) .setOperandDead(3); // Dead scc - if (Opc == AMDGPU::S_XOR_B32 || Opc == AMDGPU::V_XOR_B16_fake16_e64) { + if (Opc == AMDGPU::S_XOR_B32 || Opc == AMDGPU::V_XOR_B16_fake16_e64 || + Opc == AMDGPU::V_XOR_B16_t16_e64) { BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg) .addReg(SrcReg) .addReg(ParityRegister); @@ -6911,18 +6922,24 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, ST.getGeneration() >= AMDGPUSubtarget::GFX12 ? AMDGPU::V_ADD_F64_pseudo_e64 : AMDGPU::V_ADD_F64_e64); + case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B16_t16: + return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_AND_B16_t16_e64); case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B16: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B32); case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B32: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B32); case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B64); + case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B16_t16: + return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_OR_B16_t16_e64); case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B16: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B32); case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B32: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B32); case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B64); + case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B16_t16: + return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_XOR_B16_t16_e64); case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B16: return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_XOR_B32); case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B32: diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 8d2432e680a5b..dd9715d7f2e67 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -422,7 +422,10 @@ defvar Operations = [ WaveReduceOp<"umax", "U16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, WaveReduceOp<"max", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, WaveReduceOp<"add", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, - WaveReduceOp<"sub", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts> + WaveReduceOp<"sub", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, + WaveReduceOp<"and", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, + WaveReduceOp<"or", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>, + WaveReduceOp<"xor", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts> ]; foreach Op = Operations in { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll index b970f4a6894d0..711dddff2762c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll @@ -11,6 +11,10 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -80,52 +84,100 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX10GISEL-NEXT: global_store_short v1, v0, s[0:1] ; GFX10GISEL-NEXT: s_endpgm ; -; GFX1164DAGISEL-LABEL: uniform_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_clause 0x1 -; GFX1164DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1164DAGISEL-NEXT: s_endpgm -; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm -; -; GFX1132DAGISEL-LABEL: uniform_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_clause 0x1 -; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 -; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1132DAGISEL-NEXT: s_endpgm -; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1164DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1132DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.and.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -273,77 +325,157 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, -1 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_and_b32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1164GISEL-LABEL: divergent_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164GISEL-NEXT: s_mov_b32 s2, -1 -; GFX1164GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164GISEL-NEXT: s_and_b32 s2, s2, s4 -; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164GISEL-NEXT: ; %bb.2: -; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, -1 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_and_b32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132GISEL-LABEL: divergent_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132GISEL-NEXT: s_mov_b32 s0, -1 -; GFX1132GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132GISEL-NEXT: s_and_b32 s0, s0, s3 -; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132GISEL-NEXT: ; %bb.2: -; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_and_b32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX1164GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, s4 +; GFX1164GISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, -1 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_and_b32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s0, -1 +; GFX1132GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s0, s0, s3 +; GFX1132GISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0xffff +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_and_b16 v3.l, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-TRUE16-NEXT: s_mov_b32 s2, 0xffff +; GFX1164GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-TRUE16-NEXT: v_and_b16 v3.l, s2, s4 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, 0xffff +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s0, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_and_b16 v3.l, s1, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s1, 0xffff +; GFX1132GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-TRUE16-NEXT: s_bitset0_b32 s0, s2 +; GFX1132GISEL-TRUE16-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132GISEL-TRUE16-NEXT: v_and_b16 v3.l, s1, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132GISEL-TRUE16-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.and.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -3482,8 +3614,3 @@ endif: store i64 %combine, ptr addrspace(1) %out ret void } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX1132DAGISEL-FAKE16: {{.*}} -; GFX1132GISEL-FAKE16: {{.*}} -; GFX1164DAGISEL-FAKE16: {{.*}} -; GFX1164GISEL-FAKE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll index b5021d17699bd..1a51b7950b272 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll @@ -11,6 +11,10 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -80,52 +84,100 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX10GISEL-NEXT: global_store_short v1, v0, s[0:1] ; GFX10GISEL-NEXT: s_endpgm ; -; GFX1164DAGISEL-LABEL: uniform_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_clause 0x1 -; GFX1164DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1164DAGISEL-NEXT: s_endpgm -; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm -; -; GFX1132DAGISEL-LABEL: uniform_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_clause 0x1 -; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 -; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1132DAGISEL-NEXT: s_endpgm -; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1164DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1132DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.or.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -273,77 +325,157 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_or_b32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1164GISEL-LABEL: divergent_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164GISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164GISEL-NEXT: s_or_b32 s2, s2, s4 -; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164GISEL-NEXT: ; %bb.2: -; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_or_b32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132GISEL-LABEL: divergent_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132GISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132GISEL-NEXT: s_or_b32 s0, s0, s3 -; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132GISEL-NEXT: ; %bb.2: -; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_or_b32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-FAKE16-NEXT: s_or_b32 s2, s2, s4 +; GFX1164GISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_or_b32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-FAKE16-NEXT: s_or_b32 s0, s0, s3 +; GFX1132GISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_or_b16 v3.l, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-TRUE16-NEXT: v_or_b16 v3.l, s2, s4 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s0, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_or_b16 v3.l, s1, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s1, 0 +; GFX1132GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-TRUE16-NEXT: s_bitset0_b32 s0, s2 +; GFX1132GISEL-TRUE16-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132GISEL-TRUE16-NEXT: v_or_b16 v3.l, s1, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132GISEL-TRUE16-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.or.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -3483,8 +3615,3 @@ endif: store i64 %combine, ptr addrspace(1) %out ret void } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX1132DAGISEL-FAKE16: {{.*}} -; GFX1132GISEL-FAKE16: {{.*}} -; GFX1164DAGISEL-FAKE16: {{.*}} -; GFX1164GISEL-FAKE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll index bc423b692e607..afaa690ae4531 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll @@ -11,6 +11,10 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX8DAGISEL-LABEL: uniform_value_i16: @@ -135,73 +139,141 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v1, v0, s[0:1] ; GFX1032GISEL-NEXT: s_endpgm ; -; GFX1164DAGISEL-LABEL: uniform_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_clause 0x1 -; GFX1164DAGISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c -; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1164DAGISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: s_and_b32 s2, s2, 1 -; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164DAGISEL-NEXT: s_mul_i32 s2, s6, s2 -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1164DAGISEL-NEXT: s_endpgm -; -; GFX1164GISEL-LABEL: uniform_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_clause 0x1 -; GFX1164GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c -; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec -; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3] -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 1 -; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1164GISEL-NEXT: s_and_b32 s3, 0xffff, s6 -; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2 -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1164GISEL-NEXT: s_endpgm -; -; GFX1132DAGISEL-LABEL: uniform_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_clause 0x1 -; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1132DAGISEL-NEXT: s_and_b32 s3, s3, 1 -; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132DAGISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 -; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1] -; GFX1132DAGISEL-NEXT: s_endpgm -; -; GFX1132GISEL-LABEL: uniform_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_clause 0x1 -; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c -; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo -; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: s_and_b32 s3, s3, 1 -; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1132GISEL-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX1132GISEL-NEXT: s_mul_i32 s2, s2, s3 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1] -; GFX1132GISEL-NEXT: s_endpgm +; GFX1164DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: s_and_b32 s2, s2, 1 +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s6, s2 +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 1 +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s3, 0xffff, s6 +; GFX1164GISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_and_b32 s3, s3, 1 +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX1132DAGISEL-FAKE16-NEXT: s_endpgm +; +; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1 +; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s3, s3, 1 +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-FAKE16-NEXT: s_endpgm +; +; GFX1164DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: s_and_b32 s2, s2, 1 +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s6, s2 +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c +; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec +; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1164GISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 1 +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s3, 0xffff, s6 +; GFX1164GISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132DAGISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: s_and_b32 s3, s3, 1 +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132DAGISEL-TRUE16-NEXT: s_endpgm +; +; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1 +; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo +; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX1132GISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 1 +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1132GISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX1132GISEL-TRUE16-NEXT: s_endpgm entry: %result = call i16 @llvm.amdgcn.wave.reduce.xor.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -349,77 +421,157 @@ define void @divergent_value_i16(ptr addrspace(1) %out, i16 %in) { ; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off ; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1164DAGISEL-LABEL: divergent_value_i16: -; GFX1164DAGISEL: ; %bb.0: ; %entry -; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164DAGISEL-NEXT: s_xor_b32 s2, s2, s4 -; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164DAGISEL-NEXT: ; %bb.2: -; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1164GISEL-LABEL: divergent_value_i16: -; GFX1164GISEL: ; %bb.0: ; %entry -; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec -; GFX1164GISEL-NEXT: s_mov_b32 s2, 0 -; GFX1164GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1] -; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3 -; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3 -; GFX1164GISEL-NEXT: s_xor_b32 s2, s2, s4 -; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1164GISEL-NEXT: ; %bb.2: -; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132DAGISEL-LABEL: divergent_value_i16: -; GFX1132DAGISEL: ; %bb.0: ; %entry -; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132DAGISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132DAGISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132DAGISEL-NEXT: s_xor_b32 s0, s0, s3 -; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132DAGISEL-NEXT: ; %bb.2: -; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX1132GISEL-LABEL: divergent_value_i16: -; GFX1132GISEL: ; %bb.0: ; %entry -; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo -; GFX1132GISEL-NEXT: s_mov_b32 s0, 0 -; GFX1132GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 -; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2 -; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s2 -; GFX1132GISEL-NEXT: s_xor_b32 s0, s0, s3 -; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB1_1 -; GFX1132GISEL-NEXT: ; %bb.2: -; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off -; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1164DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-FAKE16-NEXT: s_xor_b32 s2, s2, s4 +; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1164GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-FAKE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1164GISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-FAKE16-NEXT: s_xor_b32 s2, s2, s4 +; GFX1164GISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2 +; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132DAGISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132DAGISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132DAGISEL-FAKE16-NEXT: s_xor_b32 s0, s0, s3 +; GFX1132DAGISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-FAKE16-LABEL: divergent_value_i16: +; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry +; GFX1132GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s1, exec_lo +; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s0, 0 +; GFX1132GISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-FAKE16-NEXT: s_ctz_i32_b32 s2, s1 +; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1132GISEL-FAKE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-FAKE16-NEXT: s_bitset0_b32 s1, s2 +; GFX1132GISEL-FAKE16-NEXT: s_xor_b32 s0, s0, s3 +; GFX1132GISEL-FAKE16-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1132GISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-FAKE16-NEXT: ; %bb.2: +; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s0 +; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164DAGISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164DAGISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164DAGISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164DAGISEL-TRUE16-NEXT: v_xor_b16 v3.l, s2, s4 +; GFX1164DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164DAGISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1164GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1164GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[0:1], exec +; GFX1164GISEL-TRUE16-NEXT: s_mov_b32 s2, 0 +; GFX1164GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1164GISEL-TRUE16-NEXT: s_ctz_i32_b64 s3, s[0:1] +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1164GISEL-TRUE16-NEXT: v_readlane_b32 s4, v2, s3 +; GFX1164GISEL-TRUE16-NEXT: s_bitset0_b64 s[0:1], s3 +; GFX1164GISEL-TRUE16-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1164GISEL-TRUE16-NEXT: v_xor_b16 v3.l, s2, s4 +; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1164GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1164GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1164GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132DAGISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX1132DAGISEL-TRUE16-NEXT: s_mov_b32 s1, 0 +; GFX1132DAGISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132DAGISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_bitset0_b32 s0, s2 +; GFX1132DAGISEL-TRUE16-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132DAGISEL-TRUE16-NEXT: v_xor_b16 v3.l, s1, s3 +; GFX1132DAGISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132DAGISEL-TRUE16-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132DAGISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132DAGISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1 +; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132DAGISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1132GISEL-TRUE16-LABEL: divergent_value_i16: +; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1132GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s0, exec_lo +; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s1, 0 +; GFX1132GISEL-TRUE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1 +; GFX1132GISEL-TRUE16-NEXT: s_ctz_i32_b32 s2, s0 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1132GISEL-TRUE16-NEXT: v_readlane_b32 s3, v2, s2 +; GFX1132GISEL-TRUE16-NEXT: s_bitset0_b32 s0, s2 +; GFX1132GISEL-TRUE16-NEXT: s_cmp_lg_u32 s0, 0 +; GFX1132GISEL-TRUE16-NEXT: v_xor_b16 v3.l, s1, s3 +; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1132GISEL-TRUE16-NEXT: v_readfirstlane_b32 s1, v3 +; GFX1132GISEL-TRUE16-NEXT: s_cbranch_scc1 .LBB1_1 +; GFX1132GISEL-TRUE16-NEXT: ; %bb.2: +; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1 +; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1132GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] entry: %result = call i16 @llvm.amdgcn.wave.reduce.xor.i16(i16 %in, i32 1) store i16 %result, ptr addrspace(1) %out @@ -3994,8 +4146,3 @@ endif: store i64 %combine, ptr addrspace(1) %out ret void } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX1132DAGISEL-FAKE16: {{.*}} -; GFX1132GISEL-FAKE16: {{.*}} -; GFX1164DAGISEL-FAKE16: {{.*}} -; GFX1164GISEL-FAKE16: {{.*}} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
