https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/209778
Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) >From 39ff4daaa842366c9e1980910be31bcb72b7d1b6 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 26 Jun 2026 07:47:27 +0200 Subject: [PATCH] AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (52) Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- .../AMDGPU/si-lower-control-flow-kill.ll | 2 +- ...si-lower-control-flow-unreachable-block.ll | 2 +- .../CodeGen/AMDGPU/si-lower-control-flow.mir | 2 +- .../CodeGen/AMDGPU/si-lower-i1-copies.mir | 4 +-- .../si-lower-sgpr-spills-cycle-header.mir | 4 +-- ...wer-sgpr-spills-initial-insert-in-body.mir | 2 +- ...er-sgpr-spills-initial-insert-in-latch.mir | 2 +- ...si-lower-sgpr-spills-multi-entry-cycle.mir | 4 +-- .../CodeGen/AMDGPU/si-lower-sgpr-spills.mir | 2 +- .../AMDGPU/simplifydemandedbits-recursion.ll | 2 +- .../AMDGPU/skip-branch-taildup-ret.mir | 2 +- llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll | 2 +- .../test/CodeGen/AMDGPU/spill-before-exec.mir | 2 +- .../AMDGPU/spill-csr-frame-ptr-reg-copy.ll | 2 +- .../AMDGPU/spill-empty-live-interval.mir | 2 +- .../spill-partial-csr-sgpr-live-ins.mir | 2 +- .../AMDGPU/spill-sgpr-csr-live-ins.mir | 2 +- .../CodeGen/AMDGPU/split-scalar-i64-add.ll | 2 +- .../AMDGPU/splitkit-copy-live-lanes.mir | 2 +- .../AMDGPU/splitkit-nolivesubranges.mir | 2 +- .../AMDGPU/srem-seteq-illegal-types.ll | 2 +- .../stop-tail-duplicate-cfg-intrinsic.mir | 4 +-- llvm/test/CodeGen/AMDGPU/subreg-intervals.mir | 4 +-- .../CodeGen/AMDGPU/subreg_interference.mir | 2 +- llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir | 2 +- llvm/test/CodeGen/AMDGPU/trap.ll | 36 +++++++++---------- .../CodeGen/AMDGPU/trunc-store-f64-to-f16.ll | 2 +- .../twoaddr-regsequence-keep-copy-on-use.mir | 4 +-- .../CodeGen/AMDGPU/twoaddr-regsequence.mir | 2 +- .../AMDGPU/undefined-subreg-liverange.ll | 4 +-- llvm/test/CodeGen/AMDGPU/unsupported-calls.ll | 4 +-- .../AMDGPU/urem-seteq-illegal-types.ll | 2 +- llvm/test/CodeGen/AMDGPU/valu-i1.ll | 2 +- .../AMDGPU/vector-legalizer-divergence.ll | 2 +- llvm/test/CodeGen/AMDGPU/verify-sop.mir | 4 +-- .../AMDGPU/vgpr_constant64_to_sgpr.mir | 2 +- .../virtregrewrite-undef-identity-copy.mir | 2 +- .../CodeGen/AMDGPU/vop-shrink-frame-index.mir | 4 +-- .../CodeGen/AMDGPU/vop-shrink-non-ssa.mir | 4 +-- .../waitcnt-debug-non-first-terminators.mir | 2 +- .../CodeGen/AMDGPU/waitcnt-no-redundant.mir | 2 +- llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir | 2 +- .../CodeGen/AMDGPU/widen-vselect-and-mask.ll | 2 +- llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir | 2 +- .../CodeGen/AMDGPU/zext-i64-bit-operand.ll | 2 +- llvm/test/CodeGen/AMDGPU/zext-lid.ll | 4 +-- 46 files changed, 75 insertions(+), 75 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll index 86212508882ee..083df3f0a3990 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}if_with_kill: ; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]], diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll index 3f097857cf744..28e0de8b02634 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator: ; GCN: v_cmp_eq_u32 diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir index e94ad35a45800..84cc49c19fb41 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=liveintervals,si-lower-control-flow,si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=liveintervals,si-lower-control-flow,si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s # Check that assert is not triggered diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir b/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir index f763e8c93ec18..aee14ba54125f 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -passes=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -passes=si-i1-copies -o - %s | FileCheck -check-prefixes=GCN %s --- name: lcssa_phi diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir index 0829157e079d1..469a10d47fc1e 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir @@ -1,7 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -O0 -start-before=si-lower-sgpr-spills -stop-after=regallocfast,1 -verify-machineinstrs %s -o - | FileCheck -check-prefix=WWM-REGALLOC %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -O0 -start-before=si-lower-sgpr-spills -stop-after=regallocfast,1 -verify-machineinstrs %s -o - | FileCheck -check-prefix=WWM-REGALLOC %s # When SGPR spills to a virtual VGPR lane occur in both a loop header and the latch, diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir index 3ee2b101903e3..735899506e6ac 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s --- name: sgpr_spill_initial_insert_in_body_moves_to_preheader diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir index 798a2e1e31ede..10b7a670e6384 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s --- name: sgpr_spill_initial_insert_in_latch_moves_to_preheader diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir index ff0c70a158c64..63939ff5d69ae 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -O0 -start-before=si-lower-sgpr-spills -stop-after=regallocfast,1 -verify-machineinstrs %s -o - | FileCheck -check-prefix=WWM-REGALLOC %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -O0 -start-before=si-lower-sgpr-spills -stop-after=regallocfast,1 -verify-machineinstrs %s -o - | FileCheck -check-prefix=WWM-REGALLOC %s # Ensure that for a multi-entry cycle si-lower-sgpr-spills inserts # IMPLICIT_DEF into the NCD of the cycle's entries. diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir index d30d83009d267..6d7f0623c7d18 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s # CHECK-LABEL: name: empty_entry_block # CHECK: SI_SPILL_S32_TO_VGPR diff --git a/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll b/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll index ab00b42958018..f3056b8871a33 100644 --- a/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll +++ b/llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; Check we can compile this bugpoint-reduced test without an ; infinite loop in TLI.SimplifyDemandedBits() due to failure diff --git a/llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir b/llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir index 4b5d05167d53a..a4b34780879ef 100644 --- a/llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir +++ b/llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-pre-emit-peephole -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-pre-emit-peephole -o - %s | FileCheck %s --- name: skip_branch_taildup_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll b/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll index 17ac0a826ceba..7bb2efbdf7816 100644 --- a/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll +++ b/llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; FIXME: merge with trap.ll diff --git a/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir b/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir index d500bba7119bf..27a0f9ea3a6a4 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-before-exec.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -verify-machineinstrs -debug-only=regalloc -run-pass=greedy -filetype=null %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00-- -verify-machineinstrs -debug-only=regalloc -run-pass=greedy -filetype=null %s 2>&1 | FileCheck %s --- # Check that physreg candidate is not used since cannot be spilled in a block, diff --git a/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll b/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll index 95ed6456cd52b..ac90a7cbb4189 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -stress-regalloc=1 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}spill_csr_s5_copy: ; GCN: s_mov_b32 [[FP_SCRATCH_COPY:s[0-9]+]], s33 diff --git a/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir index a55b8038d255a..75b68900a10a7 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -amdgpu-enable-rewrite-partial-reg-uses=false -amdgpu-dce-in-ra=0 -stress-regalloc=1 -start-before=register-coalescer -stop-after=greedy,1 -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -amdgpu-enable-rewrite-partial-reg-uses=false -amdgpu-dce-in-ra=0 -stress-regalloc=1 -start-before=register-coalescer -stop-after=greedy,1 -o - %s | FileCheck %s # https://bugs.llvm.org/show_bug.cgi?id=33620 --- diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir index 400bfa54980c2..e32fee6b9abb0 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s --- name: spill_partial_live_csr_sgpr_test diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir index 7b6ecd7c037c3..665b14aa6a653 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s --- name: spill_csr_sgpr_argument diff --git a/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll b/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll index b65ac0557217c..69ca7bc2dce0e 100644 --- a/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll +++ b/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() readnone diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir b/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir index d27d9ae829e91..0bfd490a0ae68 100644 --- a/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir +++ b/llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-regalloc -run-pass=greedy %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-regalloc -run-pass=greedy %s -o - | FileCheck %s --- name: zextload_global_v64i16_to_v64i64 diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir b/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir index dcac8e737cb05..a8cf32375f88e 100644 --- a/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir +++ b/llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=greedy,virtregrewriter -verify-regalloc %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=greedy,virtregrewriter -verify-regalloc %s -o - | FileCheck %s # This test aims to trigger live-range splitting at a place where %0 subranges # are all dead, but the main live-range of %0 is still alive. %0 main range is diff --git a/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll index db9df6e2f7fdd..73eea2b9ff9d6 100644 --- a/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-amd-mesa3d < %s | FileCheck %s define i1 @test_srem_odd(i29 %X) nounwind { ; CHECK-LABEL: test_srem_odd: diff --git a/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir b/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir index d257caaa2d9b8..a3ebe94e04684 100644 --- a/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir +++ b/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=early-tailduplication -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -passes=early-tailduplication -o - %s | FileCheck %s --- name: stop_duplicate_cfg_intrinsic diff --git a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir index 2d234b76689f9..3e3d4460e48b9 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir +++ b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass liveintervals -debug-only=regalloc -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 --passes='print<live-intervals>' -debug-only=regalloc -filetype=null %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass liveintervals -debug-only=regalloc -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 --passes='print<live-intervals>' -debug-only=regalloc -filetype=null %s 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK: INTERVALS diff --git a/llvm/test/CodeGen/AMDGPU/subreg_interference.mir b/llvm/test/CodeGen/AMDGPU/subreg_interference.mir index 207b848ea427f..b23fd7ff79c0f 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg_interference.mir +++ b/llvm/test/CodeGen/AMDGPU/subreg_interference.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s +# RUN: llc -o - %s -mtriple=amdgpu7.00--amdhsa -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s --- | define amdgpu_kernel void @func0() { diff --git a/llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir b/llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir index 256ac06fe6f9f..ed8f8417be3aa 100644 --- a/llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir +++ b/llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=block-placement -tail-dup-placement-threshold=2 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass=block-placement -tail-dup-placement-threshold=2 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # Check that tail duplication correctly counts instructions in a bundle. # The bundle below shall not be duplicated. diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll index ca27a389cdb5f..c377ce2bceb3d 100644 --- a/llvm/test/CodeGen/AMDGPU/trap.ll +++ b/llvm/test/CodeGen/AMDGPU/trap.ll @@ -1,27 +1,27 @@ -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00--amdhsa < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s -; RUN: llc -global-isel=1 -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00--amdhsa -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00--amdhsa -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00--amdhsa -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00--amdhsa -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; enable trap handler feature -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=+trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=+trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s ; disable trap handler feature -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s -; RUN: llc -global-isel=0 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx600 -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=-trap-handler < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00-unknown-mesa3d -mattr=-trap-handler < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s +; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap handler not supported diff --git a/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll b/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll index f157ec7be4e1b..9ba9597cc99cd 100644 --- a/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll +++ b/llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}global_truncstore_f64_to_f16: ; GCN: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir index d575be5cfd82c..4cbcfa1d552bf 100644 --- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir +++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck -check-prefix=CHECK %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=liveintervals,twoaddressinstruction -o - %s | FileCheck -check-prefix=LIS %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=twoaddressinstruction -o - %s | FileCheck -check-prefix=CHECK %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=liveintervals,twoaddressinstruction -o - %s | FileCheck -check-prefix=LIS %s # Checks that while lowering REG_SEQUENCE, undef COPY are not skipped if there is no LIS # information diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir index 8cdf34d21c8ba..953ae0600e419 100644 --- a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir +++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=liveintervals,twoaddressinstruction,register-coalescer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,register-coalescer -verify-machineinstrs -o - %s | FileCheck %s # Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE. --- diff --git a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll index a66db0456ea17..582252a590d5c 100644 --- a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll +++ b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -early-live-intervals < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 -early-live-intervals < %s | FileCheck %s ; We may have subregister live ranges that are undefined on some paths. The ; verifier should not complain about this. diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll index 675f279c367a2..61140d383a151 100644 --- a/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/unsupported-calls.ll @@ -1,5 +1,5 @@ -; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s -; RUN: not llc -mtriple=amdgcn--amdpal -mcpu=gfx600 -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s +; RUN: not llc -mtriple=amdgpu6.00-mesa-mesa3d -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s +; RUN: not llc -mtriple=amdgpu6.00--amdpal -tailcallopt < %s 2>&1 | FileCheck --check-prefix=GCN %s ; RUN: not llc -mtriple=r600-- -mcpu=cypress -tailcallopt < %s 2>&1 | FileCheck -check-prefix=R600 %s declare i32 @external_function(i32) nounwind diff --git a/llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll index 1c23a1bac9ec8..37ddd1e5d6e26 100644 --- a/llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-amd-mesa3d < %s | FileCheck %s define i1 @test_urem_odd(i13 %X) nounwind { ; CHECK-LABEL: test_urem_odd: diff --git a/llvm/test/CodeGen/AMDGPU/valu-i1.ll b/llvm/test/CodeGen/AMDGPU/valu-i1.ll index 6f20a4e290c90..0f934e7ff2303 100644 --- a/llvm/test/CodeGen/AMDGPU/valu-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/valu-i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -enable-misched -asm-verbose -disable-block-placement -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 -enable-misched -asm-verbose -disable-block-placement -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll b/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll index c414acf927a1d..5e848bc9d113f 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll +++ b/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; Tests for a bug in SelectionDAG::UpdateNodeOperands exposed by VectorLegalizer ; where divergence information is not updated. diff --git a/llvm/test/CodeGen/AMDGPU/verify-sop.mir b/llvm/test/CodeGen/AMDGPU/verify-sop.mir index c52e5624653a8..b3d7fc68d2d41 100644 --- a/llvm/test/CodeGen/AMDGPU/verify-sop.mir +++ b/llvm/test/CodeGen/AMDGPU/verify-sop.mir @@ -1,5 +1,5 @@ -# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s -# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx600 --passes='machine-function(verify)' %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgpu6.00 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgpu6.00 --passes='machine-function(verify)' %s -o - 2>&1 | FileCheck %s # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants # CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32 diff --git a/llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir b/llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir index a9d7cb495cfb3..5eb5d7f8c8996 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --global-isel=0 --run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -O0 -mtriple=amdgpu7.00-amd-amdhsa --global-isel=0 --run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s --- name: test_64imm diff --git a/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir b/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir index f181ad9a19633..6d57b9dae6e32 100644 --- a/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -start-before=greedy,0 -stop-after=virtregrewriter,1 -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -start-before=greedy,0 -stop-after=virtregrewriter,1 -verify-machineinstrs -o - %s | FileCheck %s # The undef copy of %4 is allocated to $vgpr3, and the identity copy # was deleted, and $vgpr3 was considered undef. The code to replace diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir index 4b67f10b79150..f3a55ad70eade 100644 --- a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir +++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s --- | define amdgpu_kernel void @fold_fi_vgpr() { diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir index 9e82fbb1835b7..2acdfcc30d1a3 100644 --- a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir +++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s ... # GCN-LABEL: name: fold_imm_non_ssa{{$}} # GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir index 736ede64ceba2..3d3776489b4b3 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcezero=1 %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcezero=1 %s -o - | FileCheck %s --- name: waitcnt-debug-non-first-terminators diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir index e3aad7dddc1a7..dc041ed8647b2 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s # Check that the waitcnt pass does *not* insert a redundant waitcnt instr. # In this testcase, ensure that pass does not insert redundant S_WAITCNT 3952 diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir index f8ecd01d0f8e3..4c5b6bf3a9263 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s # Check that a trivial soft waitcnt at the end of a block is deleted even if it # is followed by a meta instruction. diff --git a/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll b/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll index 35ddb7e30a2d8..906607cadede4 100644 --- a/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll +++ b/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; Check that DAGTypeLegalizer::WidenVSELECTAndMask doesn't try to ; create vselects with i64 condition masks. diff --git a/llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir b/llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir index be51e3bbc311f..604ab24bf02bc 100644 --- a/llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir +++ b/llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s # Test that si-wqm correctly handles debug instructions when computing # insertion points for SCC save/restore. Debug instructions don't have diff --git a/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll b/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll index ced74e56e0a33..f8f73c4435e51 100644 --- a/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll +++ b/llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}zext_or_operand_i64: ; GCN: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]] diff --git a/llvm/test/CodeGen/AMDGPU/zext-lid.ll b/llvm/test/CodeGen/AMDGPU/zext-lid.ll index 650fb0c3c117d..98f1b21522df7 100644 --- a/llvm/test/CodeGen/AMDGPU/zext-lid.ll +++ b/llvm/test/CodeGen/AMDGPU/zext-lid.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,O2 %s -; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,O2 %s +; RUN: llc -O0 -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; GCN-LABEL: {{^}}zext_grp_size_128: ; O2-NOT: and_b32 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
