llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-globalisel Author: Matt Arsenault (arsenm) <details> <summary>Changes</summary> Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged. Co-Authored-By: Claude <noreply@<!-- -->anthropic.com> (Claude-Opus-4.8) --- Patch is 68.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209776.diff 99 Files Affected: - (modified) llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/add_i128.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/add_i64.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/alignbit-pat.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/allow-check.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/barrier-elimination.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/bfi_nested.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/branch-uniformity.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/call-constant.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/call-constexpr.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/coalescer_remat.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/collapse-endcf.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/commute-compares.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/commute_modifiers.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/cttz-elts.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/debug-value2.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/debug_frame.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/div_v2i128.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/endpgm-dce.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extload-align.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extract-load-i1.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extract-subvector.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fabs.f64.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-cndmask.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-over-exec.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/fold-readlane.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll (+3-3) - (modified) llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/global-alias.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hoist-cond.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/indirect-call.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/ipra-regmask.ll (+4-4) - (modified) llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll (+2-2) - (modified) llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll (+1-1) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll b/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll index 974b16188b1ed..a4bb74b7c26d2 100644 --- a/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll +++ b/llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; CHECK: ;;#ASMSTART ; CHECK-NEXT: s_nop 0 diff --git a/llvm/test/CodeGen/AMDGPU/add_i128.ll b/llvm/test/CodeGen/AMDGPU/add_i128.ll index 19b05357c1f5e..5342ec89b0d69 100644 --- a/llvm/test/CodeGen/AMDGPU/add_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/add_i128.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @test_i128_vreg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) { ; GCN-LABEL: test_i128_vreg: diff --git a/llvm/test/CodeGen/AMDGPU/add_i64.ll b/llvm/test/CodeGen/AMDGPU/add_i64.ll index b4ac465f5fa0a..e14185405b610 100644 --- a/llvm/test/CodeGen/AMDGPU/add_i64.ll +++ b/llvm/test/CodeGen/AMDGPU/add_i64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s define amdgpu_kernel void @test_i64_vreg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) { ; SI-LABEL: test_i64_vreg: diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll index 38161b66fea7d..30279992a87ef 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-enable-lower-module-lds=false < %s 2> %t.err | FileCheck %s +; RUN: not llc -mtriple=amdgpu6.00 -amdgpu-enable-lower-module-lds=false < %s 2> %t.err | FileCheck %s ; RUN: FileCheck -check-prefix=ERROR %s < %t.err ; ERROR: error: unsupported expression in static initializer: addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4)) diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll index 7f892e747e245..7b54067f6db1c 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; CHECK: global.arr: ; CHECK: .zero 1024 diff --git a/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll b/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll index c21ee9842fdda..77d31967defb3 100644 --- a/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll +++ b/llvm/test/CodeGen/AMDGPU/alignbit-pat.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @alignbit_shr_pat(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) { ; GCN-LABEL: alignbit_shr_pat: diff --git a/llvm/test/CodeGen/AMDGPU/allow-check.ll b/llvm/test/CodeGen/AMDGPU/allow-check.ll index 430a8a9fb26c7..4cb6439c187ad 100644 --- a/llvm/test/CodeGen/AMDGPU/allow-check.ll +++ b/llvm/test/CodeGen/AMDGPU/allow-check.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 -global-isel=0 -fast-isel=0 | FileCheck %s -; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 -global-isel=1 -fast-isel=0 | FileCheck %s -; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx600 -global-isel=0 -fast-isel=1 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu6.00-amd-mesa3d -global-isel=0 -fast-isel=0 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu6.00-amd-mesa3d -global-isel=1 -fast-isel=0 | FileCheck %s +; RUN: llc < %s -mtriple=amdgpu6.00-amd-mesa3d -global-isel=0 -fast-isel=1 | FileCheck %s define i1 @test_runtime() local_unnamed_addr { ; CHECK-LABEL: test_runtime: diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll index 3394a287b828f..9e7a50d4d826a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-function-calls < %s | FileCheck -check-prefix=CALLS %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=CALLS %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-function-calls=0 < %s | FileCheck -check-prefix=NOCALLS %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-function-calls < %s | FileCheck -check-prefix=CALLS %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefix=CALLS %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-function-calls=0 < %s | FileCheck -check-prefix=NOCALLS %s ; RUN: llc -mtriple=r600-mesa-mesa3d < %s | FileCheck -check-prefix=NOCALLS %s ; RUN: llc -mtriple=r600-mesa-mesa3d -amdgpu-function-calls=0 < %s | FileCheck -check-prefix=NOCALLS %s diff --git a/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll b/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll index 22b5838d36c45..c1f2dd7daa984 100644 --- a/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=SI %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 diff --git a/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll b/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll index 257a51c85e6a0..6631155375172 100644 --- a/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll +++ b/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s -global-isel | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s -global-isel | FileCheck %s ; CHECK-LABEL: {{^}}unknown_wgs: ; CHECK: s_barrier diff --git a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll index 5461155d875a2..6243f9ba0741c 100644 --- a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll +++ b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s define float @v_bfi_single_nesting_level(float %x, float %y, float %z) { ; GCN-LABEL: v_bfi_single_nesting_level: diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir index 62c06ac31d474..3fdcb314366ca 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdgpu-s-branch-bits=5 -run-pass branch-relaxation %s -o - | FileCheck %s +# RUN: llc -verify-machineinstrs -mtriple=amdgpu7.00-amd-amdhsa --amdgpu-s-branch-bits=5 -run-pass branch-relaxation %s -o - | FileCheck %s --- name: branch_no_terminators diff --git a/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll b/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll index 9ee3e822cea59..a02e690b81152 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-uniformity.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s ; The branch instruction in LOOP49 has a uniform condition, but PHI instructions ; introduced by the structurizecfg pass previously caused a false divergence diff --git a/llvm/test/CodeGen/AMDGPU/call-constant.ll b/llvm/test/CodeGen/AMDGPU/call-constant.ll index d09e0b1723831..8757089cf5dad 100644 --- a/llvm/test/CodeGen/AMDGPU/call-constant.ll +++ b/llvm/test/CodeGen/AMDGPU/call-constant.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GISEL %s define amdgpu_kernel void @test_call_undef() #0 { ; SDAG-LABEL: test_call_undef: diff --git a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll index 2799efe3f16d2..53867b9031f6b 100644 --- a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GISEL %s define amdgpu_kernel void @test_bitcast_return_type_noinline() #0 { ; SDAG-LABEL: test_bitcast_return_type_noinline: diff --git a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll index 637b5f95a7b62..a640ae1635d07 100644 --- a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll +++ b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -O0 < %s | FileCheck -check-prefix=GCN_DBG %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 -O0 < %s | FileCheck -check-prefix=GCN_DBG %s define amdgpu_kernel void @test_loop(ptr addrspace(3) %ptr, i32 %n) nounwind { ; GCN-LABEL: test_loop: diff --git a/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir b/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir index 020b392fe1348..9aa7bea2c4825 100644 --- a/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir +++ b/llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s --- # GCN-LABEL: name: v_max_self_clamp_not_set_f32 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll b/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll index 44619c5516a8c..85dbfe0effd15 100644 --- a/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll +++ b/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s declare i1 @llvm.amdgcn.class.f32(float, i32) diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir index 8c8c8284791c2..6b27581e317c1 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=register-coalescer -o - %s | FileCheck %s # Test used to crash with message: # JoinVals::computeAssignment(unsigned int, (anonymous namespace)::JoinVals &): Assertion `Assignments[ValNo] != -1 && "Bad recursion?"' failed. diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir b/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir index 57189d3174c3b..6e74e5b0fa0e0 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx600 -run-pass=register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00--amdpal -run-pass=register-coalescer -o - %s | FileCheck %s # Check that this doesn't crash. Check for some legitimate output. # CHECK: S_CBRANCH_SCC1 diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir index 59280c9070cfc..c661ed5266e7c 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu6.00 -run-pass register-coalescer -o - %s | FileCheck %s # Check that %11 and %20 have been coalesced. # CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG:[0-9]+]] # CHECK: IMAGE_SAMPLE_C_D_O_V1_V11 %[[REG]] diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll index 8690f28555913..33f901b7c70cd 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll +++ b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu6.00-- -o - %s | FileCheck %s declare float @llvm.fma.f32(float, float, float) diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir index 1da5a0fbb0ab8..b7f36c5dcd542 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -passes=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -passes=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s # FIXME: This is a miscompile, and the s_or_b64s need to be preserved. diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir index dc22ca2859e0d..c434737e6dc28 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -passes=si-lower-control-flow -amdgpu-remove-redundant-endcf %s -o - | FileCheck -check-prefix=GCN %s # Make sure dbg_value doesn't change codeegn when collapsing end_cf --- diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir index 173098708e009..afa46f7877892 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s --- | define amdgpu_kernel void @call_no_explicit_exec_dependency () { diff --git a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll index 4452366c8a5fa..c18d2234470ae 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @and_i1_sext_bool(ptr addrspace(1) nocapture %arg) { ; GCN-LABEL: and_i1_sext_bool: diff --git a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll index 2783f31c0ec1d..e0bd039db2a87 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -o - %s | FileCheck %s ; The OR instruction should not be eliminated by the "OR Combine" DAG optimization. define protected amdgpu_kernel void @_Z11test_kernelPii(ptr addrspace(1) nocapture %Ad.coerce, i32 %s) local_unnamed_addr #5 { diff --git a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir index 2c24b863b154e..f20e3c9ed398b 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir +++ b/llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -verify-machineinstrs -run-pass=amdgpu-pre-ra-optimizations %s -o - | FileCheck -check-prefix=GCN %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -passes="amdgpu-pre-ra-optimizations" %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -run-pass=amdgpu-pre-ra-optimizations %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu6.00 -passes="amdgpu-pre-ra-optimizations" %s -o - | FileCheck -check-prefix=GCN %s --- name: combine_sreg64_inits diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares.ll b/llvm/test/CodeGen/AMDGPU/commute-compares.ll index 75b634fbb6190..e191fbd75e280 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-compares.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-compares.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-sdwa-peephole=0 < %s | FileC... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/209776 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
