https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/209815
>From 79624ad9c2425dbe4ed4587649b0a50e4249d9af Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 26 Jun 2026 08:02:38 +0200 Subject: [PATCH] AMDGPU: Migrate uniform target-cpu attribute tests to subarch triple (55) For tests that set the subtarget via a single uniform "target-cpu" IR function attribute, fold the cpu into the amdgpu subarch triple on the RUN lines, drop the redundant -mcpu, and remove the "target-cpu" attribute (deleting now-empty attribute groups and their references). The subtarget is unchanged, so codegen output is preserved. Co-Authored-By: Claude <[email protected]> (Claude-Opus-4.8) --- .../AMDGPU/coalescer-subregjoin-fullcopy.mir | 5 ++--- llvm/test/CodeGen/AMDGPU/debug-value.ll | 4 ++-- .../global-atomicrmw-fadd-wrong-subtarget.ll | 4 ++-- .../AMDGPU/illegal-sgpr-to-vgpr-copy.ll | 4 ++-- ...ne-sink-temporal-divergence-swdev407790.ll | 8 ++++---- llvm/test/CodeGen/AMDGPU/max-sgprs.ll | 4 ++-- .../memory-legalizer-atomic-insert-end.mir | 4 ++-- .../AMDGPU/ran-out-of-registers-errors.ll | 19 +++++++++---------- .../CodeGen/AMDGPU/sched-crash-dbg-value.mir | 6 +++--- .../CodeGen/AMDGPU/unigine-liveness-crash.ll | 4 ++-- ...fferent-addrspace-addressing-mode-loops.ll | 4 ++-- 11 files changed, 32 insertions(+), 34 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir index 0b1e2894795d5..ba7a78409aa30 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s # # See bug http://llvm.org/PR33152 for details of the bug this test is checking # for. @@ -17,11 +17,10 @@ --- | target triple = "amdgcn--amdpal" - define amdgpu_ps void @main() #0 { + define amdgpu_ps void @main() { ret void } - attributes #0 = { "target-cpu"="gfx803" } ... --- diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll b/llvm/test/CodeGen/AMDGPU/debug-value.ll index efe8f30079196..b289a484e40d0 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-value.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s %struct.wombat = type { [4 x i32], [4 x i32], [4 x i32] } @@ -85,7 +85,7 @@ declare float @barney() #2 declare void @eggs(float) #2 declare void @llvm.dbg.value(metadata, metadata, metadata) #1 -attributes #0 = { convergent nounwind "target-cpu"="gfx900" } +attributes #0 = { convergent nounwind } attributes #1 = { nounwind readnone speculatable } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll index e210abf22fb6c..a1da18969552a 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu8.03-amd-amdpal < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @global_atomic_fadd_ret_f32_wrong_subtarget(ptr addrspace(1) %ptr) #1 { ; GCN-LABEL: global_atomic_fadd_ret_f32_wrong_subtarget: @@ -74,6 +74,6 @@ define amdgpu_kernel void @global_atomic_fadd_noret_f32_wrong_subtarget(ptr addr ret void } -attributes #1 = { denormal_fpenv(float: preservesign) "target-cpu"="gfx803" "target-features"="+atomic-fadd-no-rtn-insts" } +attributes #1 = { denormal_fpenv(float: preservesign) "target-features"="+atomic-fadd-no-rtn-insts" } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll b/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll index 3e4cd5bf5f44d..f25cf6951c94b 100644 --- a/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s 2>&1 | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu9.08 < %s 2>&1 | FileCheck -check-prefix=GCN %s ; It is not illegal anymore because the SGPRs with divergent values are added with readfirstlane ; instruction in inline asm. @@ -146,4 +146,4 @@ define amdgpu_kernel void @illegal_agpr_to_sgpr_copy_v2i32() #1 { } attributes #0 = { nounwind } -attributes #1 = { nounwind "target-cpu"="gfx908" } +attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll index bca93a1d91ef1..08f1373a85ba6 100644 --- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll +++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck %s ; ModuleID = 'kernel_round1_passing.bc' source_filename = "/tmp/comgr-295d04/input/CompileSource" @@ -1100,9 +1100,9 @@ define protected amdgpu_kernel void @kernel_round1_short(ptr addrspace(1) nocapt ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare i64 @llvm.fshl.i64(i64, i64, i64) #3 -attributes #0 = { convergent mustprogress nofree nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1030" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" } -attributes #1 = { convergent nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1030" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" } -attributes #2 = { convergent norecurse nounwind "amdgpu-flat-work-group-size"="64,64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx1030" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" "uniform-work-group-size" } +attributes #0 = { convergent mustprogress nofree nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" } +attributes #1 = { convergent nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" } +attributes #2 = { convergent norecurse nounwind "amdgpu-flat-work-group-size"="64,64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32" "uniform-work-group-size" } attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } attributes #4 = { convergent nounwind willreturn memory(none) } attributes #5 = { convergent nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/max-sgprs.ll b/llvm/test/CodeGen/AMDGPU/max-sgprs.ll index b6362a2763811..2581ee87c0dbc 100644 --- a/llvm/test/CodeGen/AMDGPU/max-sgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/max-sgprs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}max_sgprs_gfx10: ; GCN: NumSgprs: 108 @@ -22,4 +22,4 @@ define amdgpu_kernel void @max_sgprs_gfx10() #0 { ret void } -attributes #0 = { nounwind "target-cpu"="gfx1010" } +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir b/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir index 5afaa7065f87f..f171652bf7b55 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn -mcpu=gfx600 -run-pass=si-memory-legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgpu8.03 -run-pass=si-memory-legalizer %s -o - | FileCheck %s --- | declare i32 @llvm.amdgcn.workitem.id.x() #0 @@ -35,7 +35,7 @@ declare void @llvm.amdgcn.end.cf(i64) attributes #0 = { nounwind readnone } - attributes #1 = { nounwind "target-cpu"="gfx803" } + attributes #1 = { nounwind } ... --- diff --git a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll index 1d23b1fd5e30f..11b5363aa7ca1 100644 --- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll +++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll @@ -1,9 +1,9 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s ; RUN: opt -passes=debugify -o %t.bc %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s +; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s ; FIXME: Asserts when using -O2 + -vgpr-regalloc=fast ; RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s @@ -18,7 +18,7 @@ ; DBGINFO-BASIC: error: {{.*}}:1:1: ran out of registers during register allocation in function 'ran_out_of_registers_general' ; DBGINFO-FAST: error: {{.*}}:3:1: ran out of registers during register allocation in function 'ran_out_of_registers_general' -define i32 @ran_out_of_registers_general(ptr addrspace(1) %ptr) #0 { +define i32 @ran_out_of_registers_general(ptr addrspace(1) %ptr) { %ld0 = load volatile i32, ptr addrspace(1) %ptr %ld1 = load volatile i32, ptr addrspace(1) %ptr %add = add i32 %ld0, %ld1 @@ -27,14 +27,14 @@ define i32 @ran_out_of_registers_general(ptr addrspace(1) %ptr) #0 { ; CHECK: error: inline assembly requires more registers than available at line 23 ; DBGINFO-CHECK: error: inline assembly requires more registers than available at line 23 -define void @ran_out_of_registers_asm_def() #0 { +define void @ran_out_of_registers_asm_def() { %asm = call { i32, i32 } asm sideeffect "; def $0 $1", "=v,=v"(), !srcloc !0 ret void } ; CHECK: error: inline assembly requires more registers than available at line 23 ; DBGINFO-CHECK: error: inline assembly requires more registers than available at line 23 -define void @ran_out_of_registers_asm_use() #0 { +define void @ran_out_of_registers_asm_use() { call void asm sideeffect "; def $0 $1", "v,v"(i32 0, i32 1), !srcloc !0 ret void } @@ -50,7 +50,7 @@ define void @ran_out_of_registers_asm_use() #0 { ; DBGINFO-BASIC: error: inline assembly requires more registers than available at line 23 ; DBGINFO-FAST: error: {{.*}}:12:1: ran out of registers during register allocation in function '@0' -define i32 @0(ptr addrspace(1) %ptr) #0 { +define i32 @0(ptr addrspace(1) %ptr) { %asm = call { i32, i32 } asm sideeffect "; def $0 $1 use $2", "=v,=v,v"(ptr addrspace(1) %ptr), !srcloc !0 %elt0 = extractvalue { i32, i32 } %asm, 0 %elt1 = extractvalue { i32, i32 } %asm, 1 @@ -58,6 +58,5 @@ define i32 @0(ptr addrspace(1) %ptr) #0 { ret i32 %add } -attributes #0 = { "target-cpu"="gfx908" } !0 = !{i32 23} diff --git a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir index 64bb7093f0679..269c384e5534e 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir @@ -1,5 +1,5 @@ -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -passes=machine-scheduler -o - %s | FileCheck %s --- | %struct.widget.0 = type { float, i32, i32 } @@ -153,7 +153,7 @@ attributes #0 = { argmemonly nounwind } attributes #1 = { nounwind readnone speculatable } - attributes #2 = { convergent nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-scratch" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="gfx900" } + attributes #2 = { convergent nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-scratch" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" } attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll b/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll index cebb8477a98d0..7f8162879842f 100644 --- a/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: llc -mtriple=amdgpu8.02 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; ; This test used to crash with the following assertion: ; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed. @@ -104,7 +104,7 @@ declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 declare <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 -attributes #0 = { nounwind "InitialPSInputAddr"="36983" "target-cpu"="tonga" } +attributes #0 = { nounwind "InitialPSInputAddr"="36983" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind readonly } attributes #3 = { nounwind } diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll index 124b7c1885649..529ba47a941c0 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -mtriple=amdgcn-- -mcpu=bonaire -loop-reduce < %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgpu7.01-- -loop-reduce < %s | FileCheck -check-prefix=OPT %s ; Test that loops with different maximum offsets for different address ; spaces are correctly handled. @@ -153,4 +153,4 @@ bb: br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hawaii" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
