https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/220051
>From 404adb2a7b3e40793260028e8ec4a4d855c432da Mon Sep 17 00:00:00 2001 From: Chinmay Deshpande <[email protected]> Date: Mon, 14 Sep 2026 10:56:32 -0700 Subject: [PATCH] [AMDGPU] Add getLDSAllocGranule to TargetParser Model LDS allocation granularity with subtarget features derived from AMDGPUGenericAnyFeature. Generic targets can select a granularity present on any covered GPU, independently of their addressable LDS size. Expose the byte-valued query for GPUKind and subarch and consolidate backend users on it. gfx9-4-generic uses gfx950's 1280-byte granule while retaining its 64 KiB addressable LDS capacity. Test feature membership, granularity assignments, query overloads and fallbacks, and generic-target LDS block rounding. Change-Id: Ic0c9345e7657ec3c6978a646628598cb7608b390 --- .../llvm/TargetParser/AMDGPUTargetParser.h | 4 ++ llvm/lib/Target/AMDGPU/AMDGPU.td | 26 +++++++- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUFeatures.td | 14 ++++ llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 4 +- llvm/lib/Target/AMDGPU/R600Processors.td | 6 +- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 14 ---- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 5 -- llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 35 +++++++++- .../CodeGen/AMDGPU/lds-size-gfx9-4-generic.ll | 33 ++++++++++ .../AMDGPUTargetDefLDSAllocGranularity.td | 42 ++++++++++++ .../TargetParser/TargetParserTest.cpp | 66 +++++++++++++++++++ 12 files changed, 226 insertions(+), 30 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/lds-size-gfx9-4-generic.ll create mode 100644 llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h index 4b0fa417c6b10..d556c85bae55a 100644 --- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h +++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h @@ -241,6 +241,10 @@ LLVM_ABI unsigned getAddressableLocalMemorySize(Triple::SubArchType SubArch, LLVM_ABI unsigned getLDSBankCount(GPUKind AK); LLVM_ABI unsigned getLDSBankCount(Triple::SubArchType SubArch); +/// \returns LDS allocation granularity in bytes. +LLVM_ABI unsigned getLDSAllocGranule(GPUKind AK); +LLVM_ABI unsigned getLDSAllocGranule(Triple::SubArchType SubArch); + /// \returns Number of SIMDs a work-group's waves run on. All four SIMDs of the /// functional block in full-SIMD mode, half of them otherwise. constexpr unsigned getNumWorkGroupSIMDs(bool FullSIMDMode) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index fb4d242dfd7a7..3ca1244c9d9e4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -1652,7 +1652,8 @@ class GCNSubtargetFeatureGeneration <string Value, def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", "southern-islands", [FeatureFP64, FeatureAddressableLocalMemorySize32768, - FeatureHalfAddressablePhysicalLocalMemory, FeatureMIMG_R128, + FeatureHalfAddressablePhysicalLocalMemory, FeatureLDSAllocGranularity256, + FeatureMIMG_R128, FeatureWavefrontSize64, FeatureSupportsWave64, FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel, @@ -1670,7 +1671,8 @@ def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", "sea-islands", - [FeatureFP64, FeatureAddressableLocalMemorySize65536, FeatureMIMG_R128, + [FeatureFP64, FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity512, FeatureMIMG_R128, FeatureWavefrontSize64, FeatureSupportsWave64, FeatureFlatAddressSpace, FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange, FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts, @@ -1690,7 +1692,8 @@ def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", "volcanic-islands", - [FeatureFP64, FeatureAddressableLocalMemorySize65536, FeatureMIMG_R128, + [FeatureFP64, FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity512, FeatureMIMG_R128, FeatureWavefrontSize64, FeatureSupportsWave64, FeatureFlatAddressSpace, FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts, FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel, @@ -1740,6 +1743,7 @@ def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9", def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10", "gfx10", [FeatureFP64, FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity512, FeatureHalfAddressablePhysicalLocalMemory, FeatureMIMG_R128, FeatureSupportsWave32, FeatureSupportsWave64, FeatureSupportsWGP, FeatureFlatAddressSpace, @@ -1774,6 +1778,7 @@ def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10", def FeatureGFX11 : GCNSubtargetFeatureGeneration<"GFX11", "gfx11", [FeatureFP64, FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity512, FeatureHalfAddressablePhysicalLocalMemory, FeatureMIMG_R128, FeatureSupportsWave32, FeatureSupportsWave64, FeatureSupportsWGP, FeatureFlatAddressSpace, Feature16BitInsts, @@ -1943,6 +1948,7 @@ def FeatureISAVersion8_1_0 : FeatureSet< def FeatureISAVersion9_0_Common : FeatureSet< [FeatureGFX9, FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity512, FeatureLDSBankCount32, FeatureImageInsts, FeatureMadMacF32Insts]>; @@ -2092,6 +2098,7 @@ def FeatureISAVersion9_4_Common : FeatureSet< def FeatureISAVersion9_5_Common : FeatureSet< !listconcat(FeatureISAVersion9_4_Common.Features, [FeatureAddressableLocalMemorySize163840, + FeatureLDSAllocGranularity1280, FeatureLDSBankCount64, FeatureFP8Insts, FeatureFP8ConversionInsts, @@ -2114,6 +2121,7 @@ def FeatureISAVersion9_4_2 : FeatureSet< !listconcat(FeatureISAVersion9_4_Common.Features, [ FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity512, FeatureLDSBankCount32, FeatureFP8Insts, FeatureFP8ConversionInsts, @@ -2125,6 +2133,7 @@ def FeatureISAVersion9_4_2 : FeatureSet< def FeatureISAVersion9_4_Generic : FeatureSet< !listconcat(FeatureISAVersion9_4_Common.Features, [FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity1280, FeatureLDSBankCount32, FeatureRequiresCOV6])>; @@ -2334,6 +2343,7 @@ def FeatureISAVersion12 : FeatureSet< FeatureSupportsWave64, FeatureSupportsWGP, FeatureBackOffBarrier, FeatureAddressableLocalMemorySize65536, + FeatureLDSAllocGranularity512, FeatureHalfAddressablePhysicalLocalMemory, FeatureLDSBankCount32, FeatureDLInsts, @@ -2492,6 +2502,7 @@ def FeatureISAVersion12_50_STRICT : FeatureSet< !listconcat(FeatureISAVersion12_50_Common.Features, [FeatureGFX1250_STRICT, FeatureAddressableLocalMemorySize327680, + FeatureLDSAllocGranularity2048, FeatureLDSBankCount64, FeatureWMMAN16Insts, FeatureVOP3PX2IncrementsVaVdstTwice, @@ -2522,6 +2533,7 @@ def FeatureISAVersion12_50_STRICT : FeatureSet< def FeatureISAVersion12_50 : FeatureSet< !listconcat(FeatureISAVersion12_50_Common.Features, [FeatureAddressableLocalMemorySize327680, + FeatureLDSAllocGranularity2048, FeatureLDSBankCount64, FeatureWMMAN16Insts, FeatureWMMAF4Insts, @@ -2553,6 +2565,7 @@ def FeatureISAVersion12_50 : FeatureSet< def FeatureISAVersion12_51 : FeatureSet< !listconcat(FeatureISAVersion12_50_Common.Features, [FeatureAddressableLocalMemorySize327680, + FeatureLDSAllocGranularity2048, FeatureLDSBankCount64, FeatureWMMAN16Insts, FeatureWMMAF4Insts, @@ -2592,6 +2605,7 @@ def FeatureISAVersion12_Generic: FeatureSet< def FeatureISAVersion12_5_Generic: FeatureSet< !listconcat(FeatureISAVersion12_50_Common.Features, [FeatureAddressableLocalMemorySize327680, + FeatureLDSAllocGranularity2048, FeatureLDSBankCount64, FeatureBlock16ConversionScaleInsts, FeatureSetregVGPRMSBFixup, @@ -2610,6 +2624,7 @@ def FeatureISAVersion13 : FeatureSet< FeatureGFX1250Insts, FeatureWaveMatchInsts, FeatureAddressableLocalMemorySize196608, + FeatureLDSAllocGranularity1024, Feature64BitLiterals, FeatureLDSBankCount32, FeatureDLInsts, @@ -3299,6 +3314,11 @@ def AMDGPUFrontendVisibleFeatures { FeatureSGPRInitBug, FeatureApertureRegs, FeatureGetDoorbellID, FeatureAGPRAlloc, Feature1536VGPRs, Feature1024AddressableVGPRs, FeatureHalfAddressablePhysicalLocalMemory, FeatureBackOffBarrier, + FeatureLDSAllocGranularity256, + FeatureLDSAllocGranularity512, + FeatureLDSAllocGranularity1024, + FeatureLDSAllocGranularity1280, + FeatureLDSAllocGranularity2048, ]; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 11c482c83f1e1..b68ab01173721 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -1440,7 +1440,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, ProgInfo.LDSSize = MFI->getLDSSize(); - unsigned LDSGranularityBytes = getLdsDwGranularity(STM) * 4; + unsigned LDSGranularityBytes = + AMDGPU::getLDSAllocGranule(STM.getTargetID().getGPUKind()); ProgInfo.LDSBlocks = alignTo(ProgInfo.LDSSize, LDSGranularityBytes) / LDSGranularityBytes; @@ -1679,8 +1680,8 @@ static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD, MD->updateHwStageMaximum( CC, ".lds_size", - (unsigned)(CurrentProgramInfo.LdsSize * getLdsDwGranularity(ST) * - sizeof(uint32_t))); + (unsigned)(CurrentProgramInfo.LdsSize * + AMDGPU::getLDSAllocGranule(ST.getTargetID().getGPUKind()))); } // This is the equivalent of EmitProgramInfoSI above, but for when the OS type diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td index 3e1655529ffbf..49c90acabb74b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td @@ -46,6 +46,20 @@ def FeatureAddressableLocalMemorySize163840 : SubtargetFeatureAddressableLocalMe def FeatureAddressableLocalMemorySize196608 : SubtargetFeatureAddressableLocalMemorySize<196608>; def FeatureAddressableLocalMemorySize327680 : SubtargetFeatureAddressableLocalMemorySize<327680>; +// A generic target uses the largest allocation granularity of its covered GPUs. +// Its feature must be present on at least one covered GPU. +class SubtargetFeatureLDSAllocGranularity <int Granularity> : AMDGPUGenericAnyFeature < + "lds-alloc-granularity-"#Granularity, + "LDSAllocationGranularity", + !cast<string>(Granularity), + "LDS allocation granularity in bytes.">; + +def FeatureLDSAllocGranularity256 : SubtargetFeatureLDSAllocGranularity<256>; +def FeatureLDSAllocGranularity512 : SubtargetFeatureLDSAllocGranularity<512>; +def FeatureLDSAllocGranularity1024 : SubtargetFeatureLDSAllocGranularity<1024>; +def FeatureLDSAllocGranularity1280 : SubtargetFeatureLDSAllocGranularity<1280>; +def FeatureLDSAllocGranularity2048 : SubtargetFeatureLDSAllocGranularity<2048>; + // Whether each wavefront size mode is available on the hardware, // independent of the active mode. def FeatureSupportsWave32 : SubtargetFeature<"supports-wave32", diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp index 723c260dc60f8..34d987cd6d266 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp @@ -185,9 +185,9 @@ GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, AMDGPU::getLocalMemorySize(getTargetID().getGPUKind(), isFullSIMDMode()); AddressableLocalMemorySize = AMDGPU::getAddressableLocalMemorySize( getTargetID().getGPUKind(), isFullSIMDMode()); - // LDS Allocation Granularity calculated in bytes from dwords + // LDS allocation granularity is in bytes. LDSAllocationGranularity = - AMDGPU::getLdsDwGranularity(*this) * sizeof(uint32_t); + AMDGPU::getLDSAllocGranule(getTargetID().getGPUKind()); HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS; HasSMulHi = getGeneration() >= AMDGPUSubtarget::GFX9; diff --git a/llvm/lib/Target/AMDGPU/R600Processors.td b/llvm/lib/Target/AMDGPU/R600Processors.td index 6637539d8c628..0daadf1423ad7 100644 --- a/llvm/lib/Target/AMDGPU/R600Processors.td +++ b/llvm/lib/Target/AMDGPU/R600Processors.td @@ -59,13 +59,15 @@ def FeatureR700 : R600SubtargetFeatureGeneration<"R700", "r700", >; def FeatureEvergreen : R600SubtargetFeatureGeneration<"EVERGREEN", "evergreen", - [FeatureFetchLimit16, FeatureAddressableLocalMemorySize32768, FeatureMadMacF32Insts] + [FeatureFetchLimit16, FeatureAddressableLocalMemorySize32768, + FeatureLDSAllocGranularity256, FeatureMadMacF32Insts] >; def FeatureNorthernIslands : R600SubtargetFeatureGeneration<"NORTHERN_ISLANDS", "northern-islands", [FeatureFetchLimit16, FeatureWavefrontSize64, - FeatureAddressableLocalMemorySize32768, FeatureMadMacF32Insts] + FeatureAddressableLocalMemorySize32768, FeatureLDSAllocGranularity256, + FeatureMadMacF32Insts] >; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 11b4dbc24c085..6200167a98354 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -3665,20 +3665,6 @@ bool isDPALU_DPP(const MCInstrDesc &OpDesc, const MCInstrInfo &MII, return hasAny64BitVGPROperands(OpDesc, MII, ST); } -unsigned getLdsDwGranularity(const MCSubtargetInfo &ST) { - if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize32768)) - return 64; - if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize65536)) - return 128; - if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize196608)) - return 256; - if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize163840)) - return 320; - if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize327680)) - return 512; - return 64; // In sync with getAddressableLocalMemorySize -} - bool isPackedSingleSGPRFP32Inst(unsigned Opc) { switch (Opc) { case AMDGPU::V_PK_ADD_F32_gfx1250: diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index e124073f0466e..a9358689514bc 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -1812,11 +1812,6 @@ getVGPRLoweringOperandTables(const MCInstrDesc &Desc); /// \returns true if a memory instruction supports scale_offset modifier. bool supportsScaleOffset(const MCInstrInfo &MII, unsigned Opcode); -/// \returns lds block size in terms of dwords. \p -/// This is used to calculate the lds size encoded for PAL metadata 3.0+ which -/// must be defined in terms of bytes. -unsigned getLdsDwGranularity(const MCSubtargetInfo &ST); - class ClusterDimsAttr { public: enum class Kind { Unknown, NoCluster, VariableDims, FixedDims }; diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp index fc027c48ca354..6cd174d0723a7 100644 --- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp +++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp @@ -528,6 +528,34 @@ AMDGPU::getBufferResourceNumRecordsWidth(Triple::SubArchType SubArch) { return getBufferResourceNumRecordsWidth(getGPUKindFromSubArch(SubArch)); } +unsigned AMDGPU::getLDSAllocGranule(GPUKind AK) { + const AMDGPUFeatureBitset &Features = getFeatureBitset(AK); + if (Features.none()) + return 256; + assert((Features.test(FEAT_LDS_ALLOC_GRANULARITY_256) || + Features.test(FEAT_LDS_ALLOC_GRANULARITY_512) || + Features.test(FEAT_LDS_ALLOC_GRANULARITY_1024) || + Features.test(FEAT_LDS_ALLOC_GRANULARITY_1280) || + Features.test(FEAT_LDS_ALLOC_GRANULARITY_2048)) && + "missing LDS allocation granularity feature"); + if (Features.test(FEAT_LDS_ALLOC_GRANULARITY_256)) + return 256; + if (Features.test(FEAT_LDS_ALLOC_GRANULARITY_512)) + return 512; + if (Features.test(FEAT_LDS_ALLOC_GRANULARITY_1024)) + return 1024; + if (Features.test(FEAT_LDS_ALLOC_GRANULARITY_1280)) + return 1280; + if (Features.test(FEAT_LDS_ALLOC_GRANULARITY_2048)) + return 2048; + + return 256; +} + +unsigned AMDGPU::getLDSAllocGranule(Triple::SubArchType SubArch) { + return getLDSAllocGranule(getGPUKindFromSubArch(SubArch)); +} + unsigned AMDGPU::getMaxWavesPerEU(GPUKind AK) { const GPUInfo *Info = getAMDGPUInfo(AK); return Info ? Info->MaxWavesPerEU : 10; @@ -564,7 +592,12 @@ static const AMDGPUFeatureBitset FrontendOnlyFeatures = { FEAT_AGPR_ALLOC, FEAT_1536_PHYSICAL_VGPRS, FEAT_HALF_ADDRESSABLE_PHYSICAL_LOCAL_MEMORY, - FEAT_1024_ADDRESSABLE_VGPRS}; + FEAT_1024_ADDRESSABLE_VGPRS, + FEAT_LDS_ALLOC_GRANULARITY_256, + FEAT_LDS_ALLOC_GRANULARITY_512, + FEAT_LDS_ALLOC_GRANULARITY_1024, + FEAT_LDS_ALLOC_GRANULARITY_1280, + FEAT_LDS_ALLOC_GRANULARITY_2048}; // Add a GPU's features (minus the frontend-only ones) to \p Features. With \p // Overwrite false, existing entries are kept so user -mattr overrides win. diff --git a/llvm/test/CodeGen/AMDGPU/lds-size-gfx9-4-generic.ll b/llvm/test/CodeGen/AMDGPU/lds-size-gfx9-4-generic.ll new file mode 100644 index 0000000000000..4e9aa8cd8a440 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/lds-size-gfx9-4-generic.ll @@ -0,0 +1,33 @@ +; RUN: llc -mtriple=amdgpu9.42-mesa-mesa3d < %s | FileCheck %s --check-prefix=GFX942 +; RUN: llc -mtriple=amdgpu9.50-mesa-mesa3d < %s | FileCheck %s --check-prefix=GFX950 +; RUN: llc -mtriple=amdgpu9.4-mesa-mesa3d < %s | FileCheck %s --check-prefix=GENERIC + +; gfx9-4-generic uses gfx950's 1280-byte granule independently of its 64 KiB +; addressable LDS capacity. gfx942 allocates the same sizes in 512-byte granules. + +@lds1280 = addrspace(3) global [320 x i32] poison, align 4 +@lds1284 = addrspace(3) global [321 x i32] poison, align 4 + +; GFX942-LABEL: one_granule: +; GFX942: granulated_lds_size = 3 +; GFX950-LABEL: one_granule: +; GFX950: granulated_lds_size = 1 +; GENERIC-LABEL: one_granule: +; GENERIC: granulated_lds_size = 1 +define amdgpu_kernel void @one_granule(i32 %index, i32 %value) { + %ptr = getelementptr [320 x i32], ptr addrspace(3) @lds1280, i32 0, i32 %index + store volatile i32 %value, ptr addrspace(3) %ptr + ret void +} + +; GFX942-LABEL: two_granules: +; GFX942: granulated_lds_size = 3 +; GFX950-LABEL: two_granules: +; GFX950: granulated_lds_size = 2 +; GENERIC-LABEL: two_granules: +; GENERIC: granulated_lds_size = 2 +define amdgpu_kernel void @two_granules(i32 %index, i32 %value) { + %ptr = getelementptr [321 x i32], ptr addrspace(3) @lds1284, i32 0, i32 %index + store volatile i32 %value, ptr addrspace(3) %ptr + ret void +} diff --git a/llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td b/llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td new file mode 100644 index 0000000000000..13136a7d00b59 --- /dev/null +++ b/llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td @@ -0,0 +1,42 @@ +// RUN: split-file %s %t +// RUN: llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/valid.td \ +// RUN: | FileCheck %t/valid.td +// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/missing.td 2>&1 \ +// RUN: | FileCheck %t/missing.td -DFILE=%t/missing.td --implicit-check-not="error:" + +//--- common.td +include "llvm/Target/Target.td" +include "AMDGPUFeatures.td" +def MyTarget : Target; + +def AMDGPUFrontendVisibleFeatures { + list<SubtargetFeature> Features = [FeatureLDSAllocGranularity512, + FeatureLDSAllocGranularity1024, + FeatureLDSAllocGranularity1280]; +} + +def GFX942 : AMDGPUProcessorModel<"gfx942", NoSchedModel, + [FeatureAddressableLocalMemorySize65536, FeatureLDSAllocGranularity512], + [9, 4, 2]>; +def GFX950 : AMDGPUProcessorModel<"gfx950", NoSchedModel, + [FeatureAddressableLocalMemorySize163840, FeatureLDSAllocGranularity1280], + [9, 5, 0]>; + +//--- valid.td +include "common.td" +// Capacity and granularity can each come from a different covered GPU. +def : AMDGPUProcessorModel<"gfx9-4-generic", NoSchedModel, + [FeatureAddressableLocalMemorySize65536, FeatureLDSAllocGranularity1280], + [9, 4, 0]> { + let CoveredGPUs = [GFX942, GFX950]; +} +// CHECK: Triple::AMDGPUSubArch9_4, AMDGPUFeatureBitset({FEAT_LDS_ALLOC_GRANULARITY_1280}), {9, 4, 0}, [[#]], 10, 65536, 32, 0}, + +//--- missing.td +include "common.td" +// CHECK: [[FILE]]:[[#@LINE+1]]:1: error: generic target 'gfx9-4-generic' exposes feature 'lds-alloc-granularity-1024' not supported by any covered GPU +def : AMDGPUProcessorModel<"gfx9-4-generic", NoSchedModel, + [FeatureAddressableLocalMemorySize65536, FeatureLDSAllocGranularity1024], + [9, 4, 0]> { + let CoveredGPUs = [GFX942, GFX950]; +} diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 3cf07ca5b0202..e4371ffa9ff2e 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -2826,6 +2826,13 @@ TEST(TargetParserTest, testAMDGPUfillAMDGPUFeatureMap) { // A capability feature is queried through the bitset only. EXPECT_FALSE(HasFeature("gfx1030", "half-addressable-physical-local-memory")); + + // LDS allocation granularity is queried through the bitset only. + EXPECT_FALSE(HasFeature("gfx600", "lds-alloc-granularity-256")); + EXPECT_FALSE(HasFeature("gfx900", "lds-alloc-granularity-512")); + EXPECT_FALSE(HasFeature("gfx950", "lds-alloc-granularity-1280")); + EXPECT_FALSE(HasFeature("gfx1310", "lds-alloc-granularity-1024")); + EXPECT_FALSE(HasFeature("gfx1250", "lds-alloc-granularity-2048")); } TEST(TargetParserTest, testAMDGPUgetFeatureBitset) { @@ -2880,6 +2887,45 @@ TEST(TargetParserTest, testAMDGPUHalfAddressableLDSFeature) { EXPECT_FALSE(Has(AMDGPU::GK_GFX1310)); } +TEST(TargetParserTest, testAMDGPULDSAllocGranularityFeatures) { + auto Has = [](AMDGPU::GPUKind AK, AMDGPU::AMDGPUFeature Feature) { + return AMDGPU::getFeatureBitset(AK).test(Feature); + }; + auto Count = [&Has](AMDGPU::GPUKind AK) { + return Has(AK, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_256) + + Has(AK, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_512) + + Has(AK, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_1024) + + Has(AK, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_1280) + + Has(AK, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_2048); + }; + + // Exactly one allocation granularity is set per GPU. + SmallVector<StringRef> AllGPUs; + AMDGPU::fillValidArchListAMDGCN(AllGPUs, Triple::NoSubArch); + for (StringRef Name : AllGPUs) { + AMDGPU::GPUKind Kind = AMDGPU::parseArchAMDGCN(Name); + if (!AMDGPU::isPseudoTarget(Kind)) + EXPECT_EQ(Count(Kind), 1) << Name; + } + + // The legacy pseudo-targets do not represent hardware. + EXPECT_EQ(Count(AMDGPU::GK_GENERIC), 0); + EXPECT_EQ(Count(AMDGPU::GK_GENERIC_HSA), 0); + + EXPECT_TRUE(Has(AMDGPU::GK_GFX600, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_256)); + EXPECT_TRUE(Has(AMDGPU::GK_GFX900, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_512)); + EXPECT_TRUE(Has(AMDGPU::GK_GFX950, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_1280)); + EXPECT_TRUE(Has(AMDGPU::GK_GFX1310, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_1024)); + EXPECT_TRUE(Has(AMDGPU::GK_GFX1250, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_2048)); + + // A generic target uses the largest allocation granularity of the GPUs it + // covers. gfx9-4-generic therefore uses gfx950's 1280-byte granule. + EXPECT_TRUE( + Has(AMDGPU::GK_GFX9_4_GENERIC, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_1280)); + EXPECT_FALSE( + Has(AMDGPU::GK_GFX9_4_GENERIC, AMDGPU::FEAT_LDS_ALLOC_GRANULARITY_512)); +} + TEST(TargetParserTest, testAMDGPUfillValidArchListAMDGCN) { SmallVector<StringRef, 0> All; AMDGPU::fillValidArchListAMDGCN(All, Triple::NoSubArch); @@ -3335,6 +3381,26 @@ TEST(TargetParserTest, testAMDGPUgetAddressableLocalMemorySize) { 65536u); } +TEST(TargetParserTest, testAMDGPUgetLDSAllocGranule) { + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GFX600), 256u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GFX900), 512u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GFX950), 1280u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GFX1310), 1024u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GFX1250), 2048u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GFX9_4_GENERIC), 1280u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_NONE), 256u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GENERIC), 256u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(AMDGPU::GK_GENERIC_HSA), 256u); + + EXPECT_EQ(AMDGPU::getLDSAllocGranule(Triple::AMDGPUSubArch600), 256u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(Triple::AMDGPUSubArch900), 512u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(Triple::AMDGPUSubArch950), 1280u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(Triple::AMDGPUSubArch1310), 1024u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(Triple::AMDGPUSubArch1250), 2048u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(Triple::AMDGPUSubArch9_4), 1280u); + EXPECT_EQ(AMDGPU::getLDSAllocGranule(Triple::NoSubArch), 256u); +} + TEST(TargetParserTest, testAMDGPUgetNumWorkGroupSIMDs) { EXPECT_EQ(AMDGPU::getNumWorkGroupSIMDs(true), 4u); EXPECT_EQ(AMDGPU::getNumWorkGroupSIMDs(false), 2u); _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
