https://bugs.llvm.org/show_bug.cgi?id=51388
Bug ID: 51388
Summary: [AMDGPU][MC][GFX10][DOC] Correct description of MIMG
address alignment
Product: libraries
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AMDGPU
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
For historical reasons MIMG address operand size must be aligned to be 16 (for
sizes greater than 8) or 8 (for sizes in the range from 5 to 7). However,
recent changes made alignment unnecessary for GFX10. See the following commits:
https://reviews.llvm.org/D103672
https://reviews.llvm.org/D103800
https://reviews.llvm.org/D103733
This should be reflected in assembler description. For example, see the
description of vaddr operand of image_atomic_add:
https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX10.html#mimg
The description states that "the size is 1, 2, 3, 4, 8 or 16 dwords. Note that
assembler currently supports a limited range of register sequences." This is no
longer valid.
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