| Issue |
174325
|
| Summary |
[DAG] visitIMINMAX - flip SMIN/SMAX <-> UMIN/UMAX if both the operand signbits are set
|
| Labels |
good first issue,
llvm:SelectionDAG
|
| Assignees |
|
| Reporter |
RKSimon
|
We currently attempt to flip SMIN/SMAX <-> UMIN/UMAX if BOTH operand signbits are zero if it improves legality.
https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6207-L6225
But as mentioned here https://github.com/llvm/llvm-project/pull/174294#discussion_r2659265414 - it is also safe to do this if BOTH signbits are set - its probably best if we replace the SignBitIsZero calls with computeKnownBits calls - and test for isStrictlyPositive / isNegative pairs directly.
Additional test coverage is almost certainly required.
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