[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.222 -> 1.223
---
Log message:

Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...


---
Diffs of the changes:  (+3 -3)

 X86ISelLowering.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.222 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.223
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.222       Fri May 26 15:37:47 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp     Fri May 26 18:10:12 2006
@@ -3326,7 +3326,7 @@
     case 1:    // ret void.
       return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
                         DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
-    case 2: {
+    case 3: {
       MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
       
       if (MVT::isVector(ArgVT)) {
@@ -3394,13 +3394,13 @@
       }
       break;
     }
-    case 3:
+    case 5:
       if (DAG.getMachineFunction().liveout_empty()) {
         DAG.getMachineFunction().addLiveOut(X86::EAX);
         DAG.getMachineFunction().addLiveOut(X86::EDX);
       }
 
-      Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2), 
+      Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(3), 
                               SDOperand());
       Copy = DAG.getCopyToReg(Copy, 
X86::EAX,Op.getOperand(1),Copy.getValue(1));
       break;



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