Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.234 -> 1.235 --- Log message: Fixed stack objects do not specify alignments, but their offsets are known. Use that information when doing the transformation to merge multiple loads into a 128-bit load. --- Diffs of the changes: (+12 -5) X86ISelLowering.cpp | 17 ++++++++++++----- 1 files changed, 12 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.234 llvm/lib/Target/X86/X86ISelLowering.cpp:1.235 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.234 Mon Jul 10 14:53:12 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jul 10 16:37:44 2006 @@ -4056,7 +4056,8 @@ return false; } -static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI) { +static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI, + const X86Subtarget *Subtarget) { GlobalValue *GV; int64_t Offset; if (isGAPlusOffset(Base, GV, Offset)) @@ -4064,7 +4065,12 @@ else { assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!"); int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex(); - return MFI->getObjectAlignment(BFI) >= 16; + if (BFI < 0) + // Fixed objects do not specify alignment, however the offsets are known. + return ((Subtarget->getStackAlignment() % 16) == 0 && + (MFI->getObjectOffset(BFI) % 16) == 0); + else + return MFI->getObjectAlignment(BFI) >= 16; } return false; } @@ -4074,7 +4080,8 @@ /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load /// if the load addresses are consecutive, non-overlapping, and in the right /// order. -static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG) { +static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, + const X86Subtarget *Subtarget) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MVT::ValueType VT = N->getValueType(0); @@ -4099,7 +4106,7 @@ } } - bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI); + bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget); if (isAlign16) return DAG.getLoad(VT, Base->getOperand(0), Base->getOperand(1), Base->getOperand(2)); @@ -4118,7 +4125,7 @@ switch (N->getOpcode()) { default: break; case ISD::VECTOR_SHUFFLE: - return PerformShuffleCombine(N, DAG); + return PerformShuffleCombine(N, DAG, Subtarget); } return SDOperand(); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits