Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.184 -> 1.185
---
Log message:
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
---
Diffs of the changes: (+3 -3)
PPCISelLowering.cpp | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.184
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.185
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.184 Wed May 24 19:57:32 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri May 26 18:10:12 2006
@@ -1160,7 +1160,7 @@
abort();
case 1:
return SDOperand(); // ret void is legal
- case 2: {
+ case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
if (MVT::isVector(ArgVT))
@@ -1180,8 +1180,8 @@
DAG.getMachineFunction().addLiveOut(ArgReg);
break;
}
- case 3:
- Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
+ case 5:
+ Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
// If we haven't noted the R3+R4 are live out, do so now.
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