Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.57 -> 1.58 X86ISelDAGToDAG.cpp updated: 1.126 -> 1.127 X86ISelLowering.cpp updated: 1.291 -> 1.292 X86InstrInfo.cpp updated: 1.71 -> 1.72 X86RegisterInfo.cpp updated: 1.176 -> 1.177 --- Log message: Matches MachineInstr changes. --- Diffs of the changes: (+47 -56) X86FloatingPoint.cpp | 29 +++++++++++------------------ X86ISelDAGToDAG.cpp | 9 +++------ X86ISelLowering.cpp | 2 +- X86InstrInfo.cpp | 22 +++++++++++----------- X86RegisterInfo.cpp | 41 +++++++++++++++++++++-------------------- 5 files changed, 47 insertions(+), 56 deletions(-) Index: llvm/lib/Target/X86/X86FloatingPoint.cpp diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.57 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.58 --- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.57 Sat Nov 11 04:21:44 2006 +++ llvm/lib/Target/X86/X86FloatingPoint.cpp Mon Nov 13 17:36:35 2006 @@ -40,6 +40,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include <algorithm> @@ -213,20 +214,12 @@ // Get dead variables list now because the MI pointer may be deleted as part // of processing! - LiveVariables::killed_iterator IB, IE; - tie(IB, IE) = LV->dead_range(MI); - - DEBUG( - const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo(); - LiveVariables::killed_iterator I = LV->killed_begin(MI); - LiveVariables::killed_iterator E = LV->killed_end(MI); - if (I != E) { - std::cerr << "Killed Operands:"; - for (; I != E; ++I) - std::cerr << " %" << MRI->getName(*I); - std::cerr << "\n"; - } - ); + SmallVector<unsigned, 8> DeadRegs; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (MO.isReg() && MO.isDead()) + DeadRegs.push_back(MO.getReg()); + } switch (Flags & X86II::FPTypeMask) { case X86II::ZeroArgFP: handleZeroArgFP(I); break; @@ -241,8 +234,8 @@ // Check to see if any of the values defined by this instruction are dead // after definition. If so, pop them. - for (; IB != IE; ++IB) { - unsigned Reg = *IB; + for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { + unsigned Reg = DeadRegs[i]; if (Reg >= X86::FP0 && Reg <= X86::FP6) { DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); freeStackSlotAfter(I, Reg-X86::FP0); @@ -762,6 +755,7 @@ unsigned Op0 = getFPReg(MI->getOperand(0)); unsigned Op1 = getFPReg(MI->getOperand(2)); + bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); // The first operand *must* be on the top of the stack. moveToTop(Op0, I); @@ -773,9 +767,8 @@ MI->getOperand(0).setReg(getSTReg(Op1)); MI->setOpcode(getConcreteOpcode(MI->getOpcode())); - // If we kill the second operand, make sure to pop it from the stack. - if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) { + if (Op0 != Op1 && KillsOp1) { // Get this value off of the register stack. freeStackSlotAfter(I, Op1); } Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.126 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.127 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.126 Sat Nov 11 04:21:44 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Nov 13 17:36:35 2006 @@ -525,8 +525,7 @@ // Finally, if we found any FP code, emit the FP_REG_KILL instruction. if (ContainsFPCode) { - BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0). - addImplicitDefsUses(); + BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0); ++NumFPKill; } } @@ -537,8 +536,7 @@ void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI) { if (Subtarget->isTargetCygwin()) - BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main"). - addImplicitDefsUses(); + BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main"); // Switch the FPU to 64-bit precision mode for better compatibility and speed. int CWFrameIdx = MFI->CreateStackObject(2, 2); @@ -949,8 +947,7 @@ // type of register here. GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass); BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0); - BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg). - addImplicitDefsUses(); + BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg); } return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val; } Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.291 llvm/lib/Target/X86/X86ISelLowering.cpp:1.292 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.291 Sat Nov 11 04:21:44 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Nov 13 17:36:35 2006 @@ -5076,7 +5076,7 @@ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); unsigned Opc = X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); - BuildMI(BB, Opc, 1).addMBB(sinkMBB).addImplicitDefsUses(); + BuildMI(BB, Opc, 1).addMBB(sinkMBB); MachineFunction *F = BB->getParent(); F->getBasicBlockList().insert(It, copy0MBB); F->getBasicBlockList().insert(It, sinkMBB); Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.71 llvm/lib/Target/X86/X86InstrInfo.cpp:1.72 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.71 Mon Oct 30 16:27:23 2006 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Mon Nov 13 17:36:35 2006 @@ -140,7 +140,7 @@ unsigned C = MI->getOperand(2).getReg(); unsigned M = MI->getOperand(3).getImmedValue(); if (!Subtarget->hasSSE2() || B != C) return 0; - return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M); + return BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M); } } @@ -157,35 +157,35 @@ case X86::INC32r: case X86::INC64_32r: assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); - return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1); + return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1); case X86::INC16r: case X86::INC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); - return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1); + return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1); case X86::DEC32r: case X86::DEC64_32r: assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); - return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1); + return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1); case X86::DEC16r: case X86::DEC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); - return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1); + return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1); case X86::ADD32rr: assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); - return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src, + return addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src, MI->getOperand(2).getReg()); case X86::ADD16rr: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); - return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src, + return addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src, MI->getOperand(2).getReg()); case X86::ADD32ri: case X86::ADD32ri8: assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, + return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, MI->getOperand(2).getImmedValue()); return 0; case X86::ADD16ri: @@ -193,7 +193,7 @@ if (DisableLEA16) return 0; assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, + return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, MI->getOperand(2).getImmedValue()); break; @@ -208,7 +208,7 @@ AM.Scale = 1 << ShAmt; AM.IndexReg = Src; unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; - return addFullAddress(BuildMI(Opc, 5, Dest), AM); + return addFullAddress(BuildMI(*this, Opc, 5, Dest), AM); } break; } @@ -239,7 +239,7 @@ unsigned A = MI->getOperand(0).getReg(); unsigned B = MI->getOperand(1).getReg(); unsigned C = MI->getOperand(2).getReg(); - return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt); + return BuildMI(*this, Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt); } default: return TargetInstrInfo::commuteInstruction(MI); Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.176 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.177 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.176 Fri Nov 10 03:13:37 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Nov 13 17:36:35 2006 @@ -165,7 +165,7 @@ const TargetInstrInfo &TII) { unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2; // Create the base instruction with the memory operand as the first part. - MachineInstrBuilder MIB = addFrameReference(BuildMI(Opcode, 4+NumOps), + MachineInstrBuilder MIB = addFrameReference(BuildMI(TII, Opcode, 4+NumOps), FrameIndex); // Loop over the rest of the ri operands, converting them over. @@ -188,7 +188,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, unsigned FrameIndex, MachineInstr *MI, const TargetInstrInfo &TII) { - MachineInstrBuilder MIB = BuildMI(Opcode, MI->getNumOperands()+3); + MachineInstrBuilder MIB = BuildMI(TII, Opcode, MI->getNumOperands()+3); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); @@ -209,9 +209,10 @@ return MIB; } -static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex, +static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, + unsigned Opcode, unsigned FrameIndex, MachineInstr *MI) { - return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0); + return addFrameReference(BuildMI(TII, Opcode, 5), FrameIndex).addImm(0); } @@ -464,13 +465,13 @@ isTwoAddrFold = true; } else if (i == 0) { // If operand 0 if (MI->getOpcode() == X86::MOV16r0) - return MakeM0Inst(X86::MOV16mi, FrameIndex, MI); + return MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI); else if (MI->getOpcode() == X86::MOV32r0) - return MakeM0Inst(X86::MOV32mi, FrameIndex, MI); + return MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI); else if (MI->getOpcode() == X86::MOV64r0) - return MakeM0Inst(X86::MOV64mi32, FrameIndex, MI); + return MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI); else if (MI->getOpcode() == X86::MOV8r0) - return MakeM0Inst(X86::MOV8mi, FrameIndex, MI); + return MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI); static const TableEntry OpcodeTable[] = { { X86::CMP16ri, X86::CMP16mi }, @@ -899,7 +900,7 @@ MachineInstr *New = 0; if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { - New=BuildMI(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr) + New=BuildMI(TII, Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr) .addReg(StackPtr).addImm(Amount); } else { assert(Old->getOpcode() == X86::ADJCALLSTACKUP); @@ -910,7 +911,7 @@ unsigned Opc = (Amount < 128) ? (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); - New = BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount); + New = BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount); } } @@ -926,7 +927,7 @@ (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); MachineInstr *New = - BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt); + BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt); MBB.insert(I, New); } } @@ -1003,15 +1004,15 @@ // more than 4k bytes in one go. Touching the stack at 4K increments is // necessary to ensure that the guard pages used by the OS virtual memory // manager are allocated in correct sequence. - MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes); + MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(NumBytes); MBB.insert(MBBI, MI); - MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); + MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); MBB.insert(MBBI, MI); } else { unsigned Opc = (NumBytes < 128) ? (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); - MI= BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes); + MI= BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes); MBB.insert(MBBI, MI); } } @@ -1023,16 +1024,16 @@ // Save EBP into the appropriate stack slot... // mov [ESP-<offset>], EBP - MI = addRegOffset(BuildMI(Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5), + MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5), StackPtr, EBPOffset+NumBytes).addReg(FramePtr); MBB.insert(MBBI, MI); // Update EBP with the new base value... if (NumBytes == SlotSize) // mov EBP, ESP - MI = BuildMI(Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr). + MI = BuildMI(TII, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr). addReg(StackPtr); else // lea EBP, [ESP+StackSize] - MI = addRegOffset(BuildMI(Is64Bit ? X86::LEA64r : X86::LEA32r, + MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::LEA64r : X86::LEA32r, 5, FramePtr), StackPtr, NumBytes-SlotSize); MBB.insert(MBBI, MI); @@ -1041,13 +1042,13 @@ // If it's main() on Cygwin\Mingw32 we should align stack as well if (Fn->hasExternalLinkage() && Fn->getName() == "main" && Subtarget->isTargetCygwin()) { - MI = BuildMI(X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align); + MI= BuildMI(TII, X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align); MBB.insert(MBBI, MI); // Probe the stack - MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align); + MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(Align); MBB.insert(MBBI, MI); - MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); + MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); MBB.insert(MBBI, MI); } } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits