Darren, another question, There are some inputs on pins 30,31,32 (called A13, A12, A11) that correspond to P45, P44, P43 on the HD6301.
Port 4 of the HD6301 is hooked up to pins 73.36,35,32,32,30,29,28 for P40-P47. I'll go look at the code, but these 3 inputs are configurable. I wonder what they do? Steve On Sun, Jan 28, 2024 at 8:21 AM Stephen Adolph <twospru...@gmail.com> wrote: > Thanks Darren. > > Now that we have the real tpdd firmware I wonder what we can do with it. > Some of those variables look tempting, like side and # of tracks. > > Another question.. it looks like was there a second unpopulated serial > port on the drive? Anything in the code on that? > P7 is unpopulated and not in the schematic, but it is there. > > Steve > > > > > > > On Sunday, January 28, 2024, Darren Clark <biggran...@gmail.com> wrote: > >> Spent some time digging through the source of the TPDD2 firmware, adding >> comments, labels, and variable names. >> >> It's documented (as far as I got so far) here: >> https://github.com/BiggRanger/Tandy_PDD/blob/master/PDD2.ASM >> >> Doesn't look like any hidden commands exist in the firmware. This is the >> list from the command table at 0xFFB9: >> >> code 0xF230 Command_FMT00_CreateDirectory >> code 0xF4D0 Command_FMT01_FileOpen >> code 0xF495 Command_FMT02_FileClose >> code 0xF69D Command_FMT03_FileRead >> code 0xF63D Command_FMT04_File_Write >> code 0xF425 Command_FMT05_FileDelete >> code 0xF212 Command_FMT06_DiskFormat >> code 0xF6F3 Command_FMT07_DriveStatus >> code 0xF137 Command_FMT_Invalid >> code 0xF75F Command_FMT23_DriveVersionInfo >> code 0xF746 Command_FMT0C_DriveCondition >> code 0xF365 Command_FMT0D_FileNameChange >> code 0xF801 Command_FMT30_SectorModeReadWrite >> code 0xF76B Command_FMT31_DriveMemorySet >> code 0xF78E Command_FMT32_DriveMemoryGet >> code 0xF757 Command_FMT33_SystemVersionInfo >> code 0xF7DC Command_FMT34_ExecuteProgram >> >> Some other interesting tables are at 0xFF67 and 0xFF6D >> >> [FF67] [80 ] [ ] Table_SysInfo: DB 0x80 ;Hard >> sector data port address MSB >> [FF68] [13 ] [ ] DB 0x13 ;Hard sector data >> port address LSB >> [FF69] [05 ] [ ] DB 0x05 ;Buffer size MSB >> [FF6A] [00 ] [ ] DB 0x00 ;Buffer size LSB >> [FF6B] [10 ] [ ] DB 0x10 ;CPU type. 0x10 = >> HD6301 >> [FF6C] [E1 ] [ ] DB 0xE1 ;Model code >> >> [FF6D] [41 ] [A ] Table_Version: DB 0x41 ;System >> Version Number MSB >> [FF6E] [10 ] [ ] DB 0x10 ;System Version >> Number LSB >> [FF6F] [01 ] [ ] DB 0x01 ;Number of sides >> [FF70] [00 ] [ ] DB 0x00 ;Number of tracks >> MSB >> [FF71] [50 ] [P ] DB 0x50 ;Number of tracks >> LSB >> [FF72] [05 ] [ ] DB 0x05 ;Sector length MSB >> [FF73] [00 ] [ ] DB 0x00 ;Sector length LSB >> [FF74] [02 ] [ ] DB 0x02 ;Sectors per track >> [FF75] [00 ] [ ] DB 0x00 ;Directory Entries MSB >> [FF76] [28 ] [( ] DB 0x28 ;Directory Entries LSB >> [FF77] [00 ] [ ] DB 0x00 ;Max files >> [FF78] [E1 ] [ ] DB 0xE1 ;Model code >> >> There is also a BAUD rate table at 0xFF85, I see logic for reading the >> dip switch setting from the CPLD at the program initialization. 2 switches >> for the BAUD rate and the other 2 for some other mode settings. Just a >> w.a.g. it almost looks like the programming on the CPLD could be the same >> on the TPPD2 as the TPPD1. It might be possible to set 9600 and 38400 BAUD, >> just guessing though as I don't have any TPDD2 hardware to play with. >> >> Overall an amazing amount of work went into this firmware. From what I >> can see, it's all hand coded and has a lot of space saving optimizations in >> it. Out of 4K of available space, there is only 15 bytes of unused space, >> and the author put his name into it (with one byte filled with a 0xFF): >> >> [FFDF] [***********] [ ] DB '(C) M.FUTAMURA',0xFF ;Author >> >> >> >> Darren Clark >> >> >> >> >> >>
