Siarhei Siamashka 写道:
I have seen your code in xserver which does the same job for downscaling, but
in nonoptimized C and with much higher impact on quality. Using JIT scaler
there can improve both image quality and performance a lot. The only my
concern is about instruction cache coherency. As ARM requires explicit
instructions cache flush for self modyfying or dynamically generated code, I
wonder if using just mmap is safe (does it flush cache for allocated region
of memory?). Maybe maemo kernel hackers/developers can help with this
information?
arm linux support flush icache by syscall "cacheflush",
qemu have this function:
static inline void flush_icache_range(unsigned long start, unsigned long
stop)
{
register unsigned long _beg __asm ("a1") = start;
register unsigned long _end __asm ("a2") = stop;
register unsigned long _flg __asm ("a3") = 0;
__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r"
(_flg));
}
you can reference kernel source arch/arm/kernel/traps.c and
include/asm-arm/unistd.h
_______________________________________________
maemo-developers mailing list
maemo-developers@maemo.org
https://maemo.org/mailman/listinfo/maemo-developers
