I was reading the memory hierarchy code and I noticed that the private L2 hierarchy instantiates write back cache controllers (mesiCache) while the shared L2 model instantiates all simpleWT controllers.
I was under the impression that most (all?) modern x86 chips have writeback caches for pretty much every level of the cache hierarchy. If I were to just switch all the caches in a shared L2 to use the mesiCache controllers, would it work? or is there some some problem at them moment that makes it so that the last level shared cache must be write through instead of write back? Thanks, Paul
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