Hi Avadh,
I tried to use all the caches as MESI cache by simply modifying the
following piece of code in memoryHierarchy.cpp:
---------------------------------
//SimpleWTCache::CacheController *l3 = new
SimpleWTCache::CacheController(0, l3_name->buf,
// this, L3_CACHE);
CacheController *l3 = new CacheController(0, l3_name->buf, this, L3_CACHE);
// l3->set_wt_disable(true);
--------------------------------
However I got the log file output as below:
........
request{Memory Request: core[0] thread[0] address[0x00007ec9db68] robid[113]
init-cycle[33269] ref-counter[1] op-type[memory_op_read] isData[1]
ownerUUID[57455] ownerRIP[0xffffffff8139135c] History[ {+C
[0]: 0
[1]: 0
[2]: 1
]initCycle[33846]
::someStructIsFull_:
What is the problem with it? Are there anything I should also modify to
achieve it?
Thanks,
Yingying
On Fri, Jan 7, 2011 at 11:45 AM, avadh patel <[email protected]> wrote:
> I am sorry for the confusing name of the cache model. The cache is
> configured as 'write-back' by setting 'wt_disable' flag to 'true' in line
> 198 of memoryHierarchy.cpp
>
> Also if you do use all the caches as MESI cache it should work.
>
> - Avadh
>
> On Thu, Jan 6, 2011 at 10:57 PM, DRAM Ninjas <[email protected]> wrote:
>
>> I was reading the memory hierarchy code and I noticed that the private L2
>> hierarchy instantiates write back cache controllers (mesiCache) while the
>> shared L2 model instantiates all simpleWT controllers.
>>
>> I was under the impression that most (all?) modern x86 chips have
>> writeback caches for pretty much every level of the cache hierarchy. If I
>> were to just switch all the caches in a shared L2 to use the mesiCache
>> controllers, would it work? or is there some some problem at them moment
>> that makes it so that the last level shared cache must be write through
>> instead of write back?
>>
>> Thanks,
>> Paul
>>
>> _______________________________________________
>> http://www.marss86.org
>> Marss86-Devel mailing list
>> [email protected]
>> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
>>
>>
>
> _______________________________________________
> http://www.marss86.org
> Marss86-Devel mailing list
> [email protected]
> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
>
>
_______________________________________________
http://www.marss86.org
Marss86-Devel mailing list
[email protected]
https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
