I've been looking through the MARSS code and found something a bit unusual. All of the functional units appear to be fully pipelined.
In the ReorderBufferEntry::issue() method, it calls clearbit(core.fu_avail, fu); in order to mark the functional unit as busy/unavailable on that cycle. Later in OutOfOrderCore::runcycle(), this is reset by the line: fu_avail = bitmask(FU_COUNT); Unless I'm missing something, wouldn't this suggest that all the functional units are fully pipelined? The Intel optimisation manual gives the latencies and issue rates of each functional unit for a lot of their processors; quite often the issue rate is not equal to 1 cycle. For my own experiments I will need to correct this and have the issue rates reflective of a real implementation. I thought I would ask first if somebody has done this already. Kind regards Tim
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