On Tue, Jan 25, 2011 at 7:20 AM, Timothy Hayes <[email protected]> wrote:
> I've been looking through the MARSS code and found something a bit unusual. > All of the functional units appear to be fully pipelined. > > In the ReorderBufferEntry::issue() method, it calls clearbit(core.fu_avail, > fu); in order to mark the functional unit as busy/unavailable on that cycle. > > Later in OutOfOrderCore::runcycle(), this is reset by the line: fu_avail = > bitmask(FU_COUNT); > > Unless I'm missing something, wouldn't this suggest that all the functional > units are fully pipelined? The Intel optimisation manual gives the latencies > and issue rates of each functional unit for a lot of their processors; quite > often the issue rate is not equal to 1 cycle. > > You are right. The default model has fully pipelined FU's which is incorrect but for simplicity its implemented this way. > For my own experiments I will need to correct this and have the issue rates > reflective of a real implementation. I thought I would ask first if somebody > has done this already. > > As per my knowledge no one has fixed this. It will be great if you can send us the patch that fix this. - Avadh Kind regards > Tim > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
_______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
