Hi, I am trying to run marss by using 3 level cache hierachy in single core model. I defined ENABLE_L3_CACHE in /marss/ptlsim/cache/memoryHierarchy.cpp file. But when I run marss, it seems there are almost no cache read or write access in L3 cache. I am wondering is there any other change I should made to enable L3 cache? Thanks.
Best zhe
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