Hi all. I would like to seek a few clarifications about the implementation of the L1 instruction cache. When I run marss simulator, I can't seem to see a solid access that is fully handled by the L1 Instruction Cache (I'm aware that the memoryHierachy solely exists to provide realistic timing data and memory usage pattern, and does not store any data). From my experiences with both the early November git repository and the v0.1.1 release (which consist of tracing the simulator with gdb) the request is apparently redirected to the L1-D cache instead (the same request for the same physicalAddress reappears 7 cycles later after a MESIBus broadcast. After 100+ cycles, the first successful memory read from the memory controller will be read by the L1-D cache. The fetch stage apparently resumes execution with a mere check for an is_i_cache_buffer_hit() test that does not check any where below the CPU controller, with the presence of an icache buffer in the cpuController.h file. So is the L1-I cache in use at all, or does it funnel all accesses to the L1-D cache?
Thank You in advance Zhong Liang Ong National University of Singapore School of Computing Computer Engineering Class of 2012 _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
