Hi Zhong, I've spent the last few weeks reading the cache code and I can't say I have seen things being funneled into the L1D cache. One thing I did is I put some stats collection into mesiCache::handle_interconnect_cb() where it checks if the message comes from the higher interconnect. If you look at the name of the sender, you should see requests from both L1I-p2p_x and L1D-p2p_x (this is what I have seen since I count icache request and dcache requests separately). Alternatively you could just look at if the sending interconnect is upperInterconnect_ (D cache) or upperInterconnect2_ (I cache).
Now granted, I don't really look at the return path to the icache or how that interacts with the core model so I can't speak to that, but I'm fairly certain that on the downward path the instruction requests stay on their own paths until they merge in the L2. Where have you seen the requests being funneled off into the L1D cache? -Paul On Mon, Feb 7, 2011 at 5:11 AM, Ong Zhong Liang <[email protected]> wrote: > Hi all. > I would like to seek a few clarifications about the implementation of the > L1 instruction cache. > When I run marss simulator, I can't seem to see a solid access that is > fully handled by the L1 Instruction Cache (I'm aware that the memoryHierachy > solely exists to provide realistic timing data and memory usage pattern, and > does not store any data). From my experiences with both the early November > git repository and the v0.1.1 release (which consist of tracing the > simulator with gdb) the request is apparently redirected to the L1-D cache > instead (the same request for the same physicalAddress reappears 7 cycles > later after a MESIBus broadcast. After 100+ cycles, the first successful > memory read from the memory controller will be read by the L1-D cache. The > fetch stage apparently resumes execution with a mere check for an > is_i_cache_buffer_hit() test that does not check any where below the CPU > controller, with the presence of an icache buffer in the cpuController.h > file. So is the L1-I cache in use at all, or does it funnel all accesses to > the L1-D cache? > > Thank You in advance > Zhong Liang Ong > National University of Singapore School of Computing > Computer Engineering Class of 2012 > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >
_______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
