Greetings, I'm fiddling with the tlb walk code in the atom core and I noticed that the addresses that are generated as part of a page table walk (root directory address, directory address, etc) are getting cached in the L1/L2 caches. I don't know if the Atom has a dedicated MMU (I would presume so), but would these intermediate addresses really ever get cached in the L1/L2 on real hardware?
It seems that the time between TLB misses is long enough that you're going to evict these entries from the L1/L2 long before you ever re-use them again. I could see how caching the address of the root directory might be useful, but anything beyond that, it seems highly unlikely that it'll ever be re-used. Curious to hear your thoughts. -Paul
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