On Sat, Apr 16, 2011 at 10:00 AM, DRAM Ninjas <[email protected]> wrote:
> Greetings, > > I'm fiddling with the tlb walk code in the atom core and I noticed that the > addresses that are generated as part of a page table walk (root directory > address, directory address, etc) are getting cached in the L1/L2 caches. I > don't know if the Atom has a dedicated MMU (I would presume so), but would > these intermediate addresses really ever get cached in the L1/L2 on real > hardware? > > Good observation here. I dont know the answer to this question. Most probably its not stored in L1/L2 caches. > It seems that the time between TLB misses is long enough that you're going > to evict these entries from the L1/L2 long before you ever re-use them > again. I could see how caching the address of the root directory might be > useful, but anything beyond that, it seems highly unlikely that it'll ever > be re-used. > > I agree on not caching all the addresses in L1/L2 caches. There is still a feature that needs to be implemented in new MemoryHierarchy that marks specific requests to not be cached in L1/L2. I have filed an bug report on github with this issue (https://github.com/avadhpatel/marss/issues/8). Thanks, Avadh Curious to hear your thoughts. > -Paul > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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