On Tue, Jun 14, 2011 at 9:04 AM, Zhe Wang <[email protected]> wrote:
> Hi, > > I have a question about the implementation of the mesi cache in marss. It > seems marss does not copy back the modified version of cacheline into the > shared last level cache in cache coherence. > > For example, in a four core processor, the L1 cache is private cache. L2 > cache is the shared last level cache. > If the L1 cache related to core1 has a read miss, and the L1 cache related > to core3 has a modified copy of that cacheline. Then the L1 cache related to > core3 should put the copy value on the bus and change the cacheline into > Share state, these action could be find in line 558-562 in file > /ptlsim/cache/cache/mesiCache.cpp file, Then this Modified value should be > copied back to the Last Level Cache, I did not find any code in marss do > this part. If this part miss, the value in last level cache and in the main > memory is not consistent with the value in L1 cache, since the state of the > requested cacheline in the L1 cache has been changed to share, so it will > not be written back to last level cache and main memory. Does anyone has > idea about this? Is this a bug of mesi cache in marss or there are > something wrong with my understanding? Thanks > > This is a bug. Lower level cache has to be updated with latest copy. If you have the patch send it to me, i'll update the repo. Thanks, Avadh > > zhe > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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