Hi, avadh, The snoop miss ration is quite low, for L1 data cache is almost 100% snoopy hits and for L1 instruction cache is 99.9% snoopy hits. So I think you are right, that should be the effect of kernel code. Thank you.
zhe On Wed, Jun 15, 2011 at 1:53 PM, avadh patel <[email protected]> wrote: > > On Tue, Jun 14, 2011 at 7:50 PM, Zhe Wang <[email protected]> wrote: > >> Hi, avadh, >> >> Thanks for your reply. >> >> Another problem I found about the mesi cache in marss is when I run >> multiple program on multicore, I think it should not have any snoop hit >> (this function is called " handle_snoop_hit "in line 505 in mesiCache.cpp), >> since this is multiple program running on multi core which is not >> multithread, so there should not be snoop hit between different cores. But >> when I debug it, I found marss do call this handle_snoop_hit function >> frequently, do you have any idea about this? Thank you. >> >> Can you add a counter to find out what is the ratio of snoop hit to snoop > miss? The sharing can be due to kernel code and data but if its too high > then there might be something wrong. > > - Avadh > > >> Best >> zhe >> >> On Tue, Jun 14, 2011 at 11:14 AM, avadh patel <[email protected]>wrote: >> >>> >>> >>> On Tue, Jun 14, 2011 at 9:04 AM, Zhe Wang <[email protected]> wrote: >>> >>>> Hi, >>>> >>>> I have a question about the implementation of the mesi cache in marss. >>>> It seems marss does not copy back the modified version of cacheline into >>>> the shared last level cache in cache coherence. >>>> >>>> For example, in a four core processor, the L1 cache is private cache. L2 >>>> cache is the shared last level cache. >>>> If the L1 cache related to core1 has a read miss, and the L1 cache >>>> related to core3 has a modified copy of that cacheline. Then the L1 cache >>>> related to core3 should put the copy value on the bus and change the >>>> cacheline into Share state, these action could be find in line 558-562 in >>>> file /ptlsim/cache/cache/mesiCache.cpp file, Then this Modified value >>>> should be copied back to the Last Level Cache, I did not find any code in >>>> marss do this part. If this part miss, the value in last level cache and >>>> in >>>> the main memory is not consistent with the value in L1 cache, since the >>>> state of the requested cacheline in the L1 cache has been changed to share, >>>> so it will not be written back to last level cache and main memory. Does >>>> anyone has idea about this? Is this a bug of mesi cache in marss or there >>>> are something wrong with my understanding? Thanks >>>> >>>> This is a bug. Lower level cache has to be updated with latest copy. If >>> you have the patch send it to me, i'll update the repo. >>> >>> Thanks, >>> Avadh >>> >>> >>>> >>>> zhe >>>> >>>> _______________________________________________ >>>> http://www.marss86.org >>>> Marss86-Devel mailing list >>>> [email protected] >>>> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >>>> >>>> >>> >> >
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