It seems like there are two load issues at the same time and they are
inserting a conflicting TLB entries. I have attached a small patch that
should fix this issue (it basically does not allow two TLB miss handling in
parallel.) I have no way to test it so please can you test this and let me
know if it works or not.
- Avadh
On Tue, Jun 28, 2011 at 9:13 AM, Francis Zhu <[email protected]> wrote:
> Hi all,
>
> I get the same error message as kuniors did when running an unmodified
> MARSS from master branch in single-core simulation.
>
> qemu-system-x86_64: ptlsim/build/core/ooocore.cpp:790: bool
> OutOfOrderModel::OutOfOrderCore::runcycle(): Assertion `0' failed.
> [vcpu 0] thread 0: WARNING: At cycle 2556928334, 3721773560 user commits:
> no instructions have committed for 16385 cycles; the pipeline could be
> deadlocked.
>
> In the attached log file, it seems to me that 2 load instructions in the
> ROB kept getting cache misses and filled the memory request pool, which
> stopped the following instructions from committing.
>
> Could anyone give me some help on this?
>
> Thanks.
>
> Francis
>
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>
diff --git a/ptlsim/core/ooocore.cpp b/ptlsim/core/ooocore.cpp
index 3a1273f..8ad000a 100644
--- a/ptlsim/core/ooocore.cpp
+++ b/ptlsim/core/ooocore.cpp
@@ -115,6 +115,8 @@ void ThreadContext::reset() {
#endif
queued_mem_lock_release_count = 0;
branchpred.init(coreid, threadid);
+
+ in_tlb_walk = 0;
}
void ThreadContext::setupTLB() {
diff --git a/ptlsim/core/ooocore.h b/ptlsim/core/ooocore.h
index 1d6e611..a2d7182 100644
--- a/ptlsim/core/ooocore.h
+++ b/ptlsim/core/ooocore.h
@@ -1448,6 +1448,7 @@ namespace OutOfOrderModel {
ITLB itlb;
void setupTLB();
W64 itlb_miss_init_cycle;
+ bool in_tlb_walk;
// Fetch-related structures
RIPVirtPhys fetchrip;
diff --git a/ptlsim/core/oooexec.cpp b/ptlsim/core/oooexec.cpp
index 18db31b..c88a484 100644
--- a/ptlsim/core/oooexec.cpp
+++ b/ptlsim/core/oooexec.cpp
@@ -1737,11 +1737,17 @@ int ReorderBufferEntry::issueload(LoadStoreQueueEntry& state, Waddr& origaddr, W
//
// TLB miss:
//
+ if(thread.in_tlb_walk) {
+ replay();
+ return ISSUE_NEEDS_REPLAY;
+ }
+
if unlikely (config.event_log_enabled) event = core.eventlog.add_load_store(EVENT_LOAD_TLB_MISS, this, sfra, addr);
cycles_left = 0;
tlb_walk_level = thread.ctx.page_table_level_count();
changestate(thread.rob_tlb_miss_list);
per_context_dcache_stats_update(core.coreid, threadid, load.dtlb.misses++);
+ thread.in_tlb_walk = 1;
return ISSUE_COMPLETED;
}
@@ -2048,6 +2054,7 @@ rob_cont:
if unlikely (config.event_log_enabled) event = core.eventlog.add_load_store(EVENT_TLBWALK_COMPLETE, this, null, virtaddr);
thread.dtlb.insert(origvirt, threadid);
+ thread.in_tlb_walk = 0;
if(logable(10)) {
ptl_logfile << "tlb miss completed for rob ", *this, " now issuing cache access\n";
diff --git a/ptlsim/core/ooopipe.cpp b/ptlsim/core/ooopipe.cpp
index c3e4feb..06e32a5 100644
--- a/ptlsim/core/ooopipe.cpp
+++ b/ptlsim/core/ooopipe.cpp
@@ -264,6 +264,7 @@ void ThreadContext::flush_pipeline() {
per_context_ooocore_stats_update(threadid,
cycles_in_pause -= pause_counter);
pause_counter = 0;
+ in_tlb_walk = 0;
}
//
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