Hi, The problem used to be in the simulation is fixed by the patch.
Thank you. Francis On Tue, Jun 28, 2011 at 2:00 PM, avadh patel <[email protected]> wrote: > It seems like there are two load issues at the same time and they are > inserting a conflicting TLB entries. I have attached a small patch that > should fix this issue (it basically does not allow two TLB miss handling in > parallel.) I have no way to test it so please can you test this and let me > know if it works or not. > > - Avadh > > On Tue, Jun 28, 2011 at 9:13 AM, Francis Zhu <[email protected]> wrote: > >> Hi all, >> >> I get the same error message as kuniors did when running an unmodified >> MARSS from master branch in single-core simulation. >> >> qemu-system-x86_64: ptlsim/build/core/ooocore.cpp:790: bool >> OutOfOrderModel::OutOfOrderCore::runcycle(): Assertion `0' failed. >> [vcpu 0] thread 0: WARNING: At cycle 2556928334, 3721773560 user commits: >> no instructions have committed for 16385 cycles; the pipeline could be >> deadlocked. >> >> In the attached log file, it seems to me that 2 load instructions in the >> ROB kept getting cache misses and filled the memory request pool, which >> stopped the following instructions from committing. >> >> Could anyone give me some help on this? >> >> Thanks. >> >> Francis >> >> _______________________________________________ >> http://www.marss86.org >> Marss86-Devel mailing list >> [email protected] >> https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel >> >> >
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