Hello, I add a simple code in MemoryController::handle_interconnect_cb() function to check the memory request dependence. In a simulation with spec2006 bzip2, I got the following dependence:
Mem_controller.numRAR: 207 #total RAR requests Mem_controller.numRAW: 45 #total RAW requests Mem_controller.numWAR: 48 #total WAR requests Mem_controller.numWAW: 5 #total WAW requests So that means the last level cache is not write back? Or I need to configure the last level cache to write back? How can I do that? Thank you very much! kuniors 2011-06-28
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