Hello, Thanks for detailed and kind reply. I have another questions about how to use write-through L1 cache and write-back shared L2 cache in multi-core environment. I know there are cache coherency protocols such as MESI and MOESI but I want to know how it should be when L1 cache is write-through. As far as I know, this kind of configuration is used in UltraSPARC processors. I tried to configure machine config file which has private L1 write-through cache for each core and shared L2 write-back cache. The upper side of those L1 caches is connected to each core by p2p bus and lower side is connected to the L2 cache by switch with directory controller. However, It seems not to work. Could any one gives me a point that how to use write-through L1 cache in multi-core configuration?
Regards, Yebin
_______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
