On Wed, Mar 28, 2012 at 5:51 PM, Yebin Lee <[email protected]> wrote:
> Hello,
>
> Thanks for detailed and kind reply.
> I have another questions about how to use write-through L1 cache and
> write-back shared L2 cache in multi-core environment.
> I know there are cache coherency protocols such as MESI and MOESI but I
> want to know how it should be when L1 cache is write-through.
> As far as I know, this kind of configuration is used in UltraSPARC
> processors.
> I tried to configure machine config file which has private L1
> write-through cache for each core and shared L2 write-back cache.
> The upper side of those L1 caches is connected to each core by p2p bus and
> lower side is connected to the L2 cache by switch with directory controller.
> However, It seems not to work.
> Could any one gives me a point that how to use write-through L1 cache in
> multi-core configuration?
>
> Current implementation of split-phase bus doesn't support caches that
don't perform Snooping. So it doesn't work with write-back caches.
I have attached a small patch that will allow split-phase bus to work with
non-snooping caches. Apply this patch and add 'option' to split-bus
configuration as shown below:
interconnects:
- type: split_bus
option:
snoop_disable: true
connections:
- L1_*: LOWER
- L2_0: UPPER
Let me know if this patch works with write-back caches or not.
- Avadh
> Regards,
> Yebin
>
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bus_with_wb_caches.patch
Description: Binary data
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