Hi are you sure of this configuration ? according to this http://www.anandtech.com/show/5058/amds-opteron-interlagos-6200/1 they have only 4 L2's and 2 L3's L1I and L1D configuration will depend how you modified MARSS' core to support buldozer architecture because the current implementation shares all the function units between the ThreadContexts -Furat
On Thu, Jun 14, 2012 at 8:36 AM, Muhammad Yasir Qadri <[email protected]>wrote: > Hi There > I have been looking into AMD Opteron 16 Core architecture and was > wondering how to simulate its cache configuration in MARSS86. The details > of which are: > L1 Cache: 16KB/core + 64KB instruction/module (i.e. 2 cores per module) > > L3 Cache: 16MB (per socket)(i.e. 16 core, or 8 modules per socket) > How can I have L1-I Cache that is shared among a core pair, L1-D Cache and > L2 Cache that is dedicated for each core? Any help in scripting that would > be highly appreciated. > Regards > > *Yasir* > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
_______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
