Hi Furat
Thanks for the prompt response. I am not exactly replicating the Opteron
however I just want the cache hierarchy, and number of cores to be the same as
the OEM. Please refer to Page#13 of:
http://sites.amd.com/us/Documents/1698_Opteron_ServerPlaybook.pdf
Yes it is a bit unusual to have an L1-I Cache having two processors to feed
(upward connection), and connected to L3 downwards; actually that is the one
thing I need your help for. Is it possible in MARSS?
Regards
Yasir
________________________________
From: Furat Afram <[email protected]>
To: Muhammad Yasir Qadri <[email protected]>
Cc: "[email protected]" <[email protected]>
Sent: Thursday, 14 June 2012, 22:11
Subject: Re: [marss86-devel] Simulating 16 Core AMD Opteron-Tricky cache
configuration
Hi
are you sure of this configuration ?
according to
this http://www.anandtech.com/show/5058/amds-opteron-interlagos-6200/1 they
have only 4 L2's and 2 L3's
L1I and L1D configuration will depend how you modified MARSS' core to support
buldozer architecture because the current implementation shares all the
function units between the ThreadContexts
-Furat
On Thu, Jun 14, 2012 at 8:36 AM, Muhammad Yasir Qadri <[email protected]>
wrote:
Hi There
>I have been looking into AMD Opteron 16 Core architecture and was wondering
>how to simulate its cache configuration in MARSS86. The details of which are:
>L1 Cache: 16KB/core + 64KB instruction/module (i.e. 2 cores per module)
L3 Cache: 16MB (per socket)(i.e. 16 core, or 8 modules per socket)
>
>How can I have L1-I Cache that is shared among a core pair, L1-D Cache and L2
>Cache that is dedicated for each core? Any help in scripting that would be
>highly appreciated.
>Regards
>Yasir
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>Marss86-Devel mailing list
>[email protected]
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>
>
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