Hi, I've gotten L3 to work with single and multiple cores. Right now I use a single L3 that utilizes a write back cache.
I've been meaning to look into some of the issues that arise with the different coherency protocols. Brendan On Thu, Mar 7, 2013 at 12:22 PM, shaoming <[email protected]> wrote: > Hi, > > Do anyone have got a machine configuration with L3 cache as shown in > the web site. I have encounter the same problem > > cycles; the pipeline could be deadlocked > qemu-system-x86_64: ptlsim/build/core/ooo-core/**ooo.cpp:917: bool > ooo::OooCore::runcycle(void*): Assertion `0' failed. > I also try to xeon configuration from the http://www.mail-archive.com/* > *[email protected].**edu/msg01074.html<http://www.mail-archive.com/[email protected]/msg01074.html>. > But this problem is still here.I have run all the splash2 benchmark and got > only ocean_nc & ocean_c results while others all have this problem. > > The branch I used is marss.dram > > Thanks, > Shaoming > > > > ______________________________**_________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected].**edu <[email protected]> > https://www.cs.binghamton.edu/**mailman/listinfo/marss86-devel<https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel> >
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