Hi all,
I compile Marss86 with following config file. The configure simulate Intel
Clovertown quad-core CPU.
/////////////// Configure file /////////////////////
# vim: filetype=yaml
#
# All core and cache configuration will be in a separate file and that will
be
# included in the final config file using 'import: [filename, ...]'
# Import files that define various core/caches
import:
- ooo_core.conf
- atom_core.conf
- l1_cache.conf
- l2_cache.conf
- moesi.conf
memory:
dram_cont1:
base: simple_dram_cont
machine:
# Use run-time option '-machine [MACHINE_NAME]' to select
clover_quad_mesi:
description: This configure simulates Clovertown machine which contains
two packages
min_contexts: 4
max_contexts: 4
cores: # The order in which core is defined is used to assign
# the cores in a machine
- type: ooo
name_prefix: ooo_
option:
threads: 1
caches:
- type: l1_128K_mesi
name_prefix: L1_I_
insts: $NUMCORES # Per core L1-I cache
option:
private: true
last_private: true
- type: l1_128K_mesi
name_prefix: L1_D_
insts: $NUMCORES # Per core L1-D cache
option:
private: true
last_private: true
- type: l2_2M_mesi
name_prefix: L2_
insts: 2 # Two packages
memory:
- type: dram_cont1
name_prefix: MEM_
insts: 1 # Single DRAM controller
option:
latency: 50 # In nano seconds
interconnects:
- type: p2p
# '$' sign is used to map matching instances like:
# cpu_0, L1_I_0
connections:
- core_$: I
L1_I_$: UPPER
- core_$: D
L1_D_$: UPPER
- type: split_bus
connections:
- L1_I_0: LOWER
L1_I_1: LOWER
L2_0: UPPER
- L1_I_2: LOWER
L1_I_3: LOWER
L2_1: UPPER
- L1_D_0: LOWER
L1_D_1: LOWER
L2_0: UPPER2
- L1_D_2: LOWER
L1_D_3: LOWER
L2_1: UPPER2
- L2_0: LOWER
L2_1: LOWER
MEM_0: UPPER
////////////////////////////////////////////////////////////////
But there is a problem where number of committed instruction is ZERO, and I
encounter with "the pipeline could be deadlocked" error after a while. You
can see part of log file:
////////////// Part of log file //////////////////////////
Start logging at level 9 in cycle 0
Completed 0 cycles, 0 commits: 0
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 118000 cycles, 0 commits: 588943
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 236000 cycles, 0 commits: 588157
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 353000 cycles, 0 commits: 584514
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 471000 cycles, 0 commits: 586772
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 590000 cycles, 0 commits: 592590
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 707000 cycles, 0 commits: 584964
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 825000 cycles, 0 commits: 588784
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
Completed 943000 cycles, 0 commits: 588781
Hz, 0 insns/sec: rip ffffffff81037eeb ffffffff81037eeb
ffffffff81037eeb 0000000000400acd
[vcpu 0] thread 0: WARNING: At cycle 1048577, 0 user commits: no
instructions have committed for 1048577 cycles; the pipeline could be
deadlocked
//////////////////////////////////////////
Could you tell me what is wrong in my defined configure which makes the
simulation be undone?
Thanks for you help is advance.
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