Hi All - I tried to mung the provided configurations to start simulating a multi-core xeon like architecture. Specifically, I would like to simulate the following: 8 cores 32 kB L1I & L1D 256 kB L2 16 MB (or 20 MB) shared L3
Unfortunately the simulator errors out with a message about the CPU pipeline possibly being deadlocked. Could someone reply with a working configuration file? The configs included in the git repo don’t have L3 caches (or they are single core). Regards, Pete Stevenson _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
