On Tue, Apr 22, 2014 at 9:00 AM, <[email protected]>wrote:
> Send Marss86-Devel mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of Marss86-Devel digest..." > > > Today's Topics: > > 1. multi-core sim (Pete Stevenson) > 2. Measurement of cache line bouncing cycles in Marss result? > (ZH) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Mon, 21 Apr 2014 12:16:57 -0700 > From: Pete Stevenson <[email protected]> > To: [email protected] > Subject: [marss86-devel] multi-core sim > Message-ID: <[email protected]> > Content-Type: text/plain; charset=windows-1252 > > Here are a Xeon config and a cache config that works for me. --Mu-Tien xeon4820.conf: ---------- # vim: filetype=yaml # # All core and cache configuration will be in a separate file and that will be # included in the final config file using 'import: [filename, ...]' # Import files that define various core/caches import: - ooo_core.conf - cache_3_level.conf memory: dram_cont: base: simple_dram_cont machine: # Use run-time option '-machine [MACHINE_NAME]' to select xeon4820: description: OOO with shared L3 min_contexts: 1 cores: # The order in which core is defined is used to assign # the cores in a machine - type: ooo name_prefix: ooo_ caches: - type: l1_32K_mesi name_prefix: L1_I_ insts: $NUMCORES # Per core L1-I cache option: private: true last_private: false - type: l1_32K_mesi name_prefix: L1_D_ insts: $NUMCORES # Per core L1-D cache option: private: true last_private: false - type: l2_256K_mesi name_prefix: L2_ insts: $NUMCORES # Per core L1-D cache option: private: true last_private: true - type: l3_16M_wb name_prefix: L3_ insts: 1 # Shared L3 config memory: - type: dram_cont name_prefix: MEM_ insts: 1 # Single DRAM controller option: latency: 50 # In nano seconds interconnects: - type: p2p connections: - core_$: I L1_I_$: UPPER - core_$: D L1_D_$: UPPER - L1_I_$: LOWER L2_$: UPPER - L1_D_$: LOWER L2_$: UPPER2 - L3_0: LOWER MEM_0: UPPER - type: split_bus connections: - L2_*: LOWER L3_0: UPPER ---------- And cache_3_level.conf looks like this: ---------- # vim: filetype=yaml cache: l1_32K_mesi: base: mesi_cache params: SIZE: 32K LINE_SIZE: 64 # bytes ASSOC: 8 LATENCY: 1 READ_PORTS: 2 WRITE_PORTS: 2 l2_256K_mesi: base: mesi_cache params: SIZE: 256K LINE_SIZE: 64 # bytes ASSOC: 8 LATENCY: 2 READ_PORTS: 1 WRITE_PORTS: 1 l3_16M_wb: base: wb_cache params: SIZE: 16M LINE_SIZE: 64 # bytes ASSOC: 16 LATENCY: 8 READ_PORTS: 1 WRITE_PORTS: 1 Hi All - > > I tried to mung the provided configurations to start simulating a > multi-core xeon like architecture. Specifically, I would like to simulate > the following: > 8 cores > 32 kB L1I & L1D > 256 kB L2 > 16 MB (or 20 MB) shared L3 > > Unfortunately the simulator errors out with a message about the CPU > pipeline possibly being deadlocked. Could someone reply with a working > configuration file? The configs included in the git repo don?t have L3 > caches (or they are single core). > > Regards, > Pete Stevenson > > > > > ------------------------------ > > Message: 2 > Date: Mon, 21 Apr 2014 17:09:09 -0600 > From: "ZH" <[email protected]> > To: <[email protected]> > Subject: [marss86-devel] Measurement of cache line bouncing cycles in > Marss result? > Message-ID: <[email protected]> > Content-Type: text/plain; charset="us-ascii" > > Hi all, > > I am trying to measure the cache line bouncing cycles in Linux on Marss. > But > in Marss result, there are so many measurement, does anyone know how to > find > out or calculate out the cache line bouncing cycles please? > > > > Regards, > > H > > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > https://www.cs.binghamton.edu/mailman/private/marss86-devel/attachments/20140421/7c842076/attachment-0001.html > > > > ------------------------------ > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > > > End of Marss86-Devel Digest, Vol 50, Issue 6 > ******************************************** >
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