Hi all,
I'm trying to modify the DRAM protocol, and doing some test with marss + dramsim2. some errors occur as follows, my focus is on DRAMSim2, so Marss is not that familiar. Who can tell me most possible reasons that happens? Is read/write, write/read dependency problem, or something else? I'm very appreciated with your answers. [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before redispatch_deadlock_recovery() 993 [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before redispatch_deadlock_recovery() 993 [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before redispatch_deadlock_recovery() 993 Completed 17000 cycles, 4280 commits: 83392 Hz, 20995 insns/sec: rip 0000000000401c1c 0000000000401274 ffffffff8100bca0 0000000000401293 [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before redispatch_deadlock_recovery() 993 [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before redispatch_deadlock_recovery() 993 [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before redispatch_deadlock_recovery() 993 [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before redispatch_deadlock_recovery() 993 Completed 33000 cycles, 4280 commits: 77853 Hz, 0 insns/sec: rip 0000000000401c1c 0000000000401274 ffffffff8100bca0 0000000000401293 ....
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