I have seen such problem when you increase your memory latency, for example to simulate NVMs. Try increasing "DISPATCH_DEAD_LOCK_COUNTDOWN_CYCLES" in ptlsim/core to a very high number.
--Ishwan On Wed, Sep 10, 2014 at 8:47 PM, 高珂 <[email protected]> wrote: > > Hi all, > > I'm trying to modify the DRAM protocol, and doing some test with marss + > dramsim2. > > some errors occur as follows, my focus is on DRAMSim2, so Marss is not > that familiar. Who can tell me most possible reasons that happens? > > Is read/write, write/read dependency problem, or something else? I'm very > appreciated with your answers. > > [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 993 > [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 993 > [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 993 > Completed 17000 cycles, 4280 commits: 83392 Hz, > 20995 insns/sec: rip 0000000000401c1c 0000000000401274 ffffffff8100bca0 > 0000000000401293 > [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 993 > [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 993 > [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 993 > [vcpu 3] thread 0: reset thread.last_commit_at_cycle to be before > redispatch_deadlock_recovery() 993 > Completed 33000 cycles, 4280 commits: 77853 Hz, > 0 insns/sec: rip 0000000000401c1c 0000000000401274 ffffffff8100bca0 > 0000000000401293 > .... > > > > > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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