Hi everyone, I'm trying to understand the dependency of IPC on (shared) L2 cache latency. I would expect naively that IPC would reduce when L2 cache latency is increased. However when I change the L2 latency to 5, 10, and 20 cycles, the IPC reported is about 4.53, 4.37, and 4.51. This is counter intuitive for me. Is there something that I'm missing here?
I appreciate any help in this regard. Thanks and regards, *Poovaiah* *Circuits and systems laboratory,* *University of Pittsburgh* Addendum: Related thread: http://thread.gmane.org/gmane.comp.emulators.marss86/319/focus=321 Details of my setup: I'm running a spec benchmark on c=4 machine for 100million instructions. The IPC is grepped from the stats file and summed together.
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