>
> Message: 1
> Date: Mon, 16 Feb 2015 19:20:21 -0500
> From: Poovaiah MP <[email protected]>
> To: [email protected]
> Subject: [marss86-devel] Dependence of IPC on cache latency
> Message-ID:
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> [email protected]>
> Content-Type: text/plain; charset="utf-8"
>
> Hi everyone,
>
> I'm trying to understand the dependency of IPC on (shared) L2 cache
> latency. I would expect naively that IPC would reduce when L2 cache latency
> is increased. However when I change the L2 latency to 5, 10, and 20 cycles,
> the IPC reported is about 4.53, 4.37, and 4.51. This is counter intuitive
> for me. Is there something that I'm missing here?
>
> I appreciate any help in this regard.
>
> Thanks and regards,
> *Poovaiah*
> *Circuits and systems laboratory,*
> *University of Pittsburgh*
>
> Addendum:
>
> Related thread:
> http://thread.gmane.org/gmane.comp.emulators.marss86/319/focus=321
>
> Details of my setup:
> I'm running a spec benchmark on c=4 machine for 100million instructions.
> The IPC is grepped from the stats file and summed together.
>

I've seen similar problem before, and for me the problem was simulation
variability. I suggest you run some more tests to find out what's going on:
(1) Use the same latency, run your experiment multiple times, and see if
the IPCs are similar. Some benchmarks have very high IPC variation.
(2) Run more instructions.
(3) Use a smaller L2. My concern for simulating small number of
instructions + large L2 is that most of your cache misses are cold misses,
so L2 latency will be less of a performance deciding factor.

Mu-Tien


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