From: Scott Rowe <[email protected]> With some panel display controller will get stuck. This only applies to MIPI Video Mode.
Signed-off-by: Scott Rowe <[email protected]> Signed-off-by: Hitesh K. Patel <[email protected]> --- drivers/staging/mrst/drv/mdfld_dsi_dpi.c | 2 +- drivers/staging/mrst/drv/mdfld_dsi_dpi.h | 3 +- drivers/staging/mrst/drv/psb_intel_display2.c | 110 +++++++++++++++++++++++-- 3 files changed, 106 insertions(+), 9 deletions(-) diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c index 515c267..ad5e68a 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c @@ -625,7 +625,7 @@ static void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config * dsi_config, REG_WRITE((MIPIA_DEVICE_READY_REG + reg_offset), 0x00000001); } -static void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output * output, int pipe) +void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output * output, int pipe) { struct drm_device * dev = output->dev; u32 reg_offset = 0; diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dpi.h b/drivers/staging/mrst/drv/mdfld_dsi_dpi.h index e6656cc..9db5e4b 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dpi.h +++ b/drivers/staging/mrst/drv/mdfld_dsi_dpi.h @@ -69,5 +69,6 @@ extern void mdfld_dsi_dpi_commit(struct drm_encoder * encoder); extern void mdfld_dsi_dpi_mode_set(struct drm_encoder * encoder, struct drm_display_mode * mode, struct drm_display_mode * adjusted_mode); - +extern void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output * output, + int pipe); #endif /*__MDFLD_DSI_DPI_H__*/ diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c b/drivers/staging/mrst/drv/psb_intel_display2.c index fa9f5e6..9951673 100644 --- a/drivers/staging/mrst/drv/psb_intel_display2.c +++ b/drivers/staging/mrst/drv/psb_intel_display2.c @@ -25,6 +25,8 @@ */ #include "mdfld_dsi_dbi.h" +#include "mdfld_dsi_dpi.h" +//#include "mdfld_dsi_output.h" #ifdef CONFIG_MDFLD_DSI_DPU #include "mdfld_dsi_dbi_dpu.h" #endif @@ -515,12 +517,18 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) int dspcntr_reg = DSPACNTR; int dspbase_reg = MRST_DSPABASE; int pipeconf_reg = PIPEACONF; + u32 pipestat_reg = PIPEASTAT; u32 gen_fifo_stat_reg = GEN_FIFO_STAT_REG; u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; + u32 mipi_enable_reg = MIPIA_DEVICE_READY_REG; u32 temp; bool enabled; int timeout = 0; + struct drm_encoder * encoder; + struct drm_connector * connector; + struct mdfld_dsi_config * dsi_config; + struct mdfld_dsi_dpi_output * dpi_output; PSB_DEBUG_ENTRY("mode = %d, pipe = %d \n", mode, pipe); @@ -545,9 +553,11 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) dspcntr_reg = DSPCCNTR; dspbase_reg = MDFLD_DSPCBASE; pipeconf_reg = PIPECCONF; + pipestat_reg = PIPECSTAT; pipeconf = dev_priv->pipeconf2; dspcntr = dev_priv->dspcntr2; gen_fifo_stat_reg = GEN_FIFO_STAT_REG + MIPIC_REG_OFFSET; + mipi_enable_reg = MIPIA_DEVICE_READY_REG + MIPIC_REG_OFFSET; break; default: DRM_ERROR("Illegal Pipe Number. \n"); @@ -592,24 +602,110 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode) } } - /* Enable the pipe */ - temp = REG_READ(pipeconf_reg); - if ((temp & PIPEACONF_ENABLE) == 0) { - REG_WRITE(pipeconf_reg, pipeconf); + if((pipe == 0) && + (is_panel_vid_or_cmd(dev) == MDFLD_DSI_ENCODER_DPI)) { + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if(!connector) { + PSB_DEBUG_ENTRY("NULL connector.\n"); + continue; + } - /* Wait for for the pipe enable to take effect. */ - mdfldWaitForPipeEnable(dev, pipe); + encoder = connector->encoder; + + if(!encoder){ + PSB_DEBUG_ENTRY("NULL encoder.\n"); + continue; + } + + if (encoder->crtc != crtc) { + PSB_DEBUG_ENTRY("Encoder CRTC doesn't match CRTC.\n"); + continue; + } + + PSB_DEBUG_ENTRY("Encoder is %x\n", (unsigned int)encoder); + + if (pipe) { + PSB_DEBUG_ENTRY("Using config 1.\n"); + dsi_config = dev_priv->dsi_configs[1]; + } + else { + PSB_DEBUG_ENTRY("Using config 0.\n"); + dsi_config = dev_priv->dsi_configs[0]; + } + + PSB_DEBUG_ENTRY("dsi encoder is %x\n", (unsigned int)&dsi_config->encoder->base); + + if (dsi_config->type != MDFLD_DSI_ENCODER_DPI) + continue; + + if(&dsi_config->encoder->base != encoder) + continue; + + dpi_output = (struct mdfld_dsi_dpi_output *)&dsi_config->encoder->base; + mdfld_dsi_dpi_turn_on(dpi_output, pipe); + } /*end of list_for_each_entry*/ } /* Enable the plane */ temp = REG_READ(dspcntr_reg); if ((temp & DISPLAY_PLANE_ENABLE) == 0) { REG_WRITE(dspcntr_reg, - temp | DISPLAY_PLANE_ENABLE); + temp | DISPLAY_PLANE_ENABLE); /* Flush the plane changes */ REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); } + /* Enable the pipe */ + temp = REG_READ(pipeconf_reg); + if ((temp & PIPEACONF_ENABLE) == 0) { + REG_WRITE(pipeconf_reg, pipeconf); + + /* Wait for for the pipe enable to take effect. */ + mdfldWaitForPipeEnable(dev, pipe); + } + + /*workaround for sighting 3741701 Random X blank display*/ + /*perform w/a in video mode only on pipe A or C*/ + if ((pipe == 0) && + (is_panel_vid_or_cmd(dev) == MDFLD_DSI_ENCODER_DPI)) { + REG_WRITE(pipestat_reg, REG_READ(pipestat_reg)); + msleep(100); + if(PIPE_VBLANK_STATUS & REG_READ(pipestat_reg)) { + printk(KERN_ALERT "OK"); + } else { + printk(KERN_ALERT "STUCK!!!!"); + /*shutdown controller*/ + temp = REG_READ(dspcntr_reg); + REG_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); + REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); + /*mdfld_dsi_dpi_shut_down(dev, pipe);*/ + REG_WRITE(0xb048, 1); + msleep(100); + temp = REG_READ(pipeconf_reg); + temp &= ~PIPEACONF_ENABLE; + REG_WRITE(pipeconf_reg, temp); + msleep(100); /*wait for pipe disable*/ + /*printk(KERN_ALERT "70008 is %x\n", REG_READ(0x70008)); + printk(KERN_ALERT "b074 is %x\n", REG_READ(0xb074));*/ + REG_WRITE(mipi_enable_reg, 0); + msleep(100); + printk(KERN_ALERT "70008 is %x\n", REG_READ(0x70008)); + printk(KERN_ALERT "b074 is %x\n", REG_READ(0xb074)); + REG_WRITE(0xb004, REG_READ(0xb004)); + /* try to bring the controller back up again*/ + REG_WRITE(mipi_enable_reg, 1); + temp = REG_READ(dspcntr_reg); + REG_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); + REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); + /*mdfld_dsi_dpi_turn_on(dev, pipe);*/ + REG_WRITE(0xb048, 2); + msleep(100); + temp = REG_READ(pipeconf_reg); + temp |= PIPEACONF_ENABLE; + REG_WRITE(pipeconf_reg, temp); + } + } + psb_intel_crtc_load_lut(crtc); /* Give the overlay scaler a chance to enable -- 1.7.1 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
